A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single switched capacitors per input line.

Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single switched capacitors per input line.

A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.

Methods and systems for an analog-to-digital converter (ADC) with constant common mode voltage may include in an ADC comprising a sampling switch on a first input line to the ADC, a sampling switch on a second input line to the ADC, N switched capacitor pairs and M single switched capacitors on the first input line, and N switched capacitor pairs and M single switched capacitors on the second input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the switched capacitor pairs between a reference voltage (Vref) and ground based on the compared voltage levels, and iteratively switching the single switched capacitors between ground and voltages that are a fraction of Vref, which may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single switched capacitors per input line.

A circuit can include a voltage comparator V.sub.d having a first input, a second input, and an output; a first plurality of capacitors C.sub.p[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with a common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a first input voltage V.sub.inp, a reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; a second plurality of capacitors C.sub.n[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator V.sub.d, wherein each top plate is also switchably electrically coupled with the common mode voltage V.sub.cm, and wherein each bottom plate is switchably electrically coupled between a second input voltage V.sub.inn, the reference voltage V.sub.ref, the common mode voltage V.sub.cm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator V.sub.d.

Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2.sup.n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2.sup.n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

A current-steering digital-to-analog converter may include dual current switch modules configured to receive digital input bits representative of desired analog output, and each dual current switch module may be controlled by one of the digital input bits. Each digital input bit may be represented by differential signals. The positive input and the negative input to drive two separate current switches in the dual current switch module may be separated, which may make the switching transition noise generated in the two current switches have a 180 degree phase difference. The output currents of these two current switches may be summed in proper phase to add the in-phase signal currents while canceling out the 180 degree out-of-phase switching noises generated in the two current switches. The 2.sup.nd order harmonic distortion and other higher even order harmonic distortions due to the common mode switching noise may be greatly reduced.