Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

An analog-to-digital converter (ADC) includes receiving an analog input voltage signal, converting the analog input voltage signal to a first digital value and an analog residue signal, converting the analog residue signal to a time value representing the analog residue signal, and converting the time value to a second digital value. The first digital value and the second digital value are combined into a digital output signal representing the analog input voltage signal.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

Systems and methods are provided for implementing an analog-to-digital converter. In some embodiments, the analog-to-digital converter comprises a first-stage quantizer, a second-stage quantizer, and a noise cancellation filter. The first-stage quantizer is configured to receive an analog input signal and generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal. The second-stage quantizer is configured to receive the residual signal, to determine a first-stage quantization error based on the residual signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the first-stage quantization error. The noise cancellation filter is configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal comprising a quantization error component less that the first-stage quantization error.

A delta-sigma modulator. The delta-sigma modulator includes a loop filter (LF) and a digital-to-analog converter (DAC) connected to an input of the LF. The delta-sigma modulator also includes an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC. The delta-sigma modulator also includes a second order noise coupling circuit (NC) connected to the ASAR and the DAC.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a comparator coupled to the main circuit. The main circuit may: transfer the input signal by an input transfer block, filter an error signal by a loop filter, and combine the transferred input signal and the filtered error signal to form a combined signal. The comparator may quantize the combined signal to provide the output signal, wherein the error signal may reflect a difference between the combined signal and the output signal.

Systems and methods are provided for implementing an analog-to-digital converter. In some embodiments, the analog-to-digital converter comprises a first-stage quantizer, a second-stage quantizer, and a noise cancellation filter. The first-stage quantizer is configured to receive an analog input signal and generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal. The second-stage quantizer is configured to receive the residual signal, to determine a first-stage quantization error based on the residual signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the first-stage quantization error. The noise cancellation filter is configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal comprising a quantization error component less than the first-stage quantization error.

Transition smoothing apparatus for reducing spurious input to a system under feedback control connected to a control loop. The apparatus includes a loop filter to integrate an error between an input signal applied to the loop filter and an output signal of the system under feedback control, an analog-to-digital converter to provide digitized integrated error values, a controller to generate output values supplied to the system under feedback control in response to the digitized integrated error values and in a start-up sequence to control a feedback digital-to-analog converter according to the digitized integrated error values to supply a first control signal to the loop filter and control the system under feedback control to generate a second control signal, and an alignment detector to detect phase alignment between the first control signal and the second control signal to control a smooth transition into closed loop operation of the control loop.