This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S.sub.IN) and outputs a time-encoded output signal (S.sub.OUT). A filter arrangement receives the input signal and also a feedback signal (S.sub.FB) from the TEM output, and generates a filtered signal (S.sub.FIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S.sub.PWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (S.sub.IN) and outputs a time-encoded output signal (S.sub.OUT). A filter arrangement receives the input signal and also a feedback signal (S.sub.FB) from the TEM output, and generates a filtered signal (S.sub.FIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (S.sub.PWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (701) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.

A system may include an output stage for driving a load at an output of the output stage, a pulse-width modulation mode path configured to pre-drive the output stage in a first mode of operation, a linear mode path configured to pre-drive the output stage in a second mode of operation and a loop filter coupled at its input to the output of the output stage and coupled at its output to both of the pulse-width modulation mode path and the linear mode path. The pulse-width modulation mode path and the linear mode path may be configured such that a first transfer function between the output of the loop filter and the output of the output stage is substantially equivalent to a second transfer function between the output of the loop filter and the output of the output stage

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).

An amplifier circuit comprising: a delta-PWM-modulator, a three-level-DAC, a loop-integrator, and a comparator. The delta-PWM-modulator receives a digital-input-signal; and processes the digital-input-signal and a modulator-triangular-signal to generate a delta-pulse-width-modulation-signal. The delta-pulse-width-modulation-signal is representative of the difference between a square-wave-carrier-signal and a digital-pulse-width-modulation of the digital-input-signal. The three-level-DAC receives the delta-pulse-width-modulation-signal from the delta-PWM-modulator and provides a three-level-analog-signal. The loop-integrator comprises: a virtual-ground-node-terminal configured to receive: (i) the three-level-analog-signal from the three-level DAC; and (ii) a feedback-signal from an output stage of the amplifier circuit via a feedback loop; and an integrator-output-terminal configured to provide a loop-integrator-output-signal. The comparator comprises a comparator-input-terminal configured to receive the loop-integrator-output-signal; a comparator-reference-terminal configured to receive a triangular-reference-signal that corresponds to the integral of the square-wave-carrier-signal; and a comparator-output-terminal configured to provide a drive-signal suitable for driving an output-stage of the amplifier circuit.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronized to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronized to the first clock signal (CLK.sub.1).

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.

This application relates to time-encoding modulators (301,700) having a self-oscillating modulator module configured to receive an input signal and output a pulse-width modulated signal (S.sub.PWM) where the pulse-width modulated signal is synchronised to a first clock signal (CLK.sub.1). A hysteretic comparator module (302) located in a feedforward path is configured to generate the time encoded signal (S.sub.PWM) at a first node (304) based on the input signal (S.sub.IN) and a feedback signal (S.sub.FB). A feedback path is coupled to the first node to provide the feedback signal, which is either applied to an input of the hysteretic comparator module via a loop filter (701) in the feedback path or applied to the feedforward path prior to a loop filter (202) upstream of the hysteretic comparator module (302). The hysteretic comparator module (302) is configured such that any change in state of the time encoded signal at the first node is synchronised to the first clock signal (CLK.sub.1).