Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R.sub.1, to obtain an encoded first bit sequence, where 0≤R.sub.1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R.sub.2, where 0≤R.sub.2≤R.sub.1≤1.

An LDPC decoding method of a received signal including a plurality of received symbols is provided. A decoding apparatus selects a perturbation space in which perturbation is to be performed based on a code length of the received signal and a maximum number of perturbation rounds indicating a number of perturbation rounds that can be performed, and performs a perturbation round. The decoding apparatus performs perturbation on a corresponding received symbol among the plurality of received symbols in each perturbation round, and decodes the received signal on which the perturbation has been performed. The decoding apparatus determines that decoding is successful when there is a perturbation round in which a decoding result of the received signal satisfies a predetermined condition.

A method and apparatus are provided for decoding a plurality of codewords from a received binary bitstream. A first decoding stage processes each of the codewords with a first iterative decoding algorithm based on forward error-correction information of the codewords. A second decoding stage processes selected ones of the codewords with a second iterative decoding algorithm, which is based on forward error-correction information in the selected ones of the codewords. Each codeword selected for the second decoding stage is selected in response to an exit from the decoding of that codeword without the production of a decoded codeword. The second iterative decoding algorithm is configured to enable a greater number of iterations of decoding per codeword than the first iterative decoding algorithm.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A method and a device of selecting a base graph of a low-density parity-check code are provided. The method includes: acquiring a data information length and a channel coding rate of to-be-encoded data; determining a target base graph selection strategy according to the data information length and an information length range of a base graph; determining a target base graph for the to-be-encoded data according to the target base graph selection strategy and the channel coding rate.

Disclosed are a decoding method and a decoding device. The decoding method includes: performing a permutation processing on a receiving sequence and a generator matrix to obtain a permuted receiving sequence and an intermediate generator matrix according to a reliability of each bit of the receiving sequence; performing a Gaussian elimination processing on the intermediate generator matrix to obtain a systematic generator matrix generator matrix; performing a hard-decision decoding on the permuted receiving sequence to obtain a hard-decision decoding sequence; in response to determining a preset decoding end condition is not achieved, selecting a target error pattern from an error pattern set; and generating a decoding result based on the target error pattern, the hard-decision decoding sequence, and the systematic generator matrix. The decoding method can ensure the decoding performance and reduce the decoding complexity.

The present disclosure relates to low-density parity-check (LDPC) encoding methods and apparatus. One example method includes encoding k information bits by using a submatrix of ((nk)/Z+j) rows and (n/Z+j) columns at an upper left corner of a check matrix H based on a first transmission code rate R satisfying R=k/(n+jZ), obtaining a first codeword including the k information bits and (nk+jZ) redundant bits, and sending the first codeword to a receive end.

Disclosed are a decoding method and a decoding device. The decoding method includes: performing a permutation processing on a receiving sequence and a generator matrix to obtain a permuted receiving sequence and an intermediate generator matrix according to a reliability of each bit of the receiving sequence; performing a Gaussian elimination processing on the intermediate generator matrix to obtain a systematic generator matrix generator matrix; performing a hard-decision decoding on the permuted receiving sequence to obtain a hard-decision decoding sequence; in response to determining a preset decoding end condition is not achieved, selecting a target error pattern from an error pattern set; and generating a decoding result based on the target error pattern, the hard-decision decoding sequence, and the systematic generator matrix. The decoding method can ensure the decoding performance and reduce the decoding complexity.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

The present disclosure relates to low-density parity-check (LDPC) encoding methods and apparatus. One example method includes obtaining k information bits to be sent to a receive end, performing LDPC encoding on the k information bits by using a submatrix of ((n?k)/Z+j) rows and (n/Z+j) columns at an upper left corner of a check matrix H based on a first transmission code rate R satisfying R=k/(n+j?Z), obtaining a first codeword including the k information bits and (n?k+j?Z) redundant bits, and sending the first codeword to the receive end.