A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

For example, an EDMG STA may generate an LDPC coded bit stream for a user based on data bits for the user in an EDMG PPDU, the LDPC coded bit stream for the user including a concatenation of a plurality of LDPC codewords, a count of the plurality of LDPC codewords is based at least on a codeword length for the user and on a code rate for the user; generate encoded and padded bits for the user by concatenating the LDPC coded bit stream with a plurality of coded pad zero bits, a count of the coded pad zero bits is based at least on a count of one or more spatial streams for the user and on the count of the plurality of LDPC codewords for the user; and distribute the encoded and padded bits for the user to the one or more spatial streams for the user.

An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 17280 bits is interleaved in units of 360-bit bit groups 0 to 47. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

For example, an EDMG STA may generate an LDPC coded bit stream for a user based on data bits for the user in an EDMG PPDU, the LDPC coded bit stream for the user including a concatenation of a plurality of LDPC codewords, a count of the plurality of LDPC codewords is based at least on a codeword length for the user and on a code rate for the user; generate encoded and padded bits for the user by concatenating the LDPC coded bit stream with a plurality of coded pad zero bits, a count of the coded pad zero bits is based at least on a count of one or more spatial streams for the user and on the count of the plurality of LDPC codewords for the user; and distribute the encoded and padded bits for the user to the one or more spatial streams for the user.

For example, an EDMG STA may generate an LDPC coded bit stream for a user based on data bits for the user in an EDMG PPDU, the LDPC coded bit stream for the user including a concatenation of a plurality of LDPC codewords, a count of the plurality of LDPC codewords is based at least on a codeword length for the user and on a code rate for the user; generate encoded and padded bits for the user by concatenating the LDPC coded bit stream with a plurality of coded pad zero bits, a count of the coded pad zero bits is based at least on a count of one or more spatial streams for the user and on the count of the plurality of LDPC codewords for the user; and distribute the encoded and padded bits for the user to the one or more spatial streams for the user.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.