Patent classifications
H03M13/1157
High-rate long LDPC codes
Methods and devices for encoding source words and decoding codewords wherein encoding a source word includes: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector
APPARATUS AND METHOD FOR HANDLING A DATA ERROR IN A MEMORY SYSTEM
A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.
Method and System for Generating Parity Check Matrix for Low-Density Parity Check Codes
A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix.
TRANSMISSION METHOD AND RECEPTION METHOD
In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A,114B), LDPC encoded data formed by LDPC encoding blocks (102A,102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).
LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 7/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 7/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Encoding method, decoding method, encoding apparatus, and decoding apparatus
An encoding method, an encoding apparatus, a decoding method, and a decoding apparatus are provided. The encoding method includes: determining a size of a shift matrix based on a length of an information sequence and a length of an identifier sequence; constructing a check matrix based on the size of the shift matrix and a base matrix; and performing low-density parity-check LDPC encoding on the information sequence and the identifier sequence based on the check matrix. The identifier sequence is a non-all-zero sequence. Because the encoded codeword includes information of the identifier sequence, a receive device can identify whether information corresponding to the encoded codeword is addressed to the receive device, thereby improving information processing efficiency in the transmission.
Transmitting apparatus and transmission method, receiving apparatus and reception method, and program
LDPC coding is executed using a check matrix of an LDPC code whose code length is 736 bits and whose code rate is 1/4, and modulation is executed using a repetition unit that has an LDPC code obtained by the LDPC coding, repeatedly arranged therein. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the parity matrix portion has a stepwise structure, the information matrix portion is indicated by a check matrix initial value table, and the check matrix initial value table is a predetermined table indicating positions of elements of “1” of the information matrix portion for each eight columns. This technique is applicable to, for example, information transmission using the LDPC code.