A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.

A method for accelerating bit error correction in a receiver in a radio communication network, wherein the receiver is configured to update soft bit values associated with each code bit of a block code based on parallel parity checks. The method includes receiving a block code encoded message, and for any group of two or more rows of a parity-check matrix of the block code: when the two or more rows are non-overlapping: combining the two or more rows in a row group for parallel updating, updating, in parallel, the parity checks of the row group for the received message, and forming a message estimate based on the updated parity checks. Corresponding computer program product, apparatus, and receiver are also disclosed.

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

A decoding method and apparatus, a network device, and a storage medium are provided. The method includes: receiving data before de-interleaving and soft bit encoding locations; dividing the data before de-interleaving to obtain first data banks; acquiring punctured data, and obtaining second data banks according to the punctured data, wherein the data before de-interleaving and the punctured data are determined in encoded data according to the soft bit encoding locations; and performing decoding according to the soft bit encoding locations, the first data banks and the second data banks, so as to obtain decoded data.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method.

According to some embodiments, a method for use in a wireless transmitter of a wireless communication network comprises encoding information bits using a purity check matrix (PCM) and transmitting the encoded information bits to a wireless receiver. The parity check matrix (PCM) is optimized according to two or more approximate cycle extrinsic message degree (ACE) constraints. In some embodiments, a first portion of the PCM is optimized according to a first ACE constraint and a second portion of the PCM is optimized according to a second ACE constraint.

An LDPC code encoding method and a communication apparatus are described that provide increased redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. A check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.