Techniques for processing bits associated with an N multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the N multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the N multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.

An operation method of a LPC decoder includes: initializing variable nodes of a Tanner graph representing a parity check matrix; performing a check node update to check nodes of the Tanner graph based on variable node values of the variable nodes; performing a variable node update when there are USC nodes among the updated check nodes as a result of the check node update; and repeating the performing of the check node update and the variable node update when there are USC nodes as the result of the check node update, wherein the performing of the variable node update includes: selecting among the variable nodes a predetermined number of variable nodes having a USC value greater than a threshold; and flipping the variable node values of the selected variable nodes, and wherein the USC value is a number of the USC nodes linked to one of the variable nodes.

An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.

A communication system includes a data source to receive a block of bits, a memory to store a set of distribution matchers. Each distribution matcher is associated with a probability mass function (PMF) to match equally likely input bits to a fixed number of output bits with values distributed according to the PMF of the distribution matcher. Each distribution matcher is associated with a selection probability, such that a sum of joint probabilities of all distribution matchers equals a target PMF. A joint probability of a distribution matcher is a product of PMF of the distribution matcher with the selection probability of the distribution matcher. The communication system also includes a shaping mapper to select the distribution matcher from the set of distribution matchers with the selection probability and to map the block of bits to a block of shaped bits with a non-uniform distribution using the selected distribution matcher and a transmitter front end to transmit the block of shaped bits over a communication channel, such that bits in a sequence of the blocks of shaped bits are distributed according to the target PMF.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes, in group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bit. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence, the present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Provided is a method for receiving data in a receiver that performs decoding using a non-binary Low Density Parity Check (LDPC) code. The method includes generating a message vector for each symbol by demodulating received data; determining data characteristics and channel characteristics of the received data; determining the number of vector elements to be used for decoding among vector elements of the message vector using at least one of the data characteristics and the channel characteristics; and selecting vector elements according to the determined number of vector elements, and decoding the received data using the selected vector elements.

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives d.sub.c input lists U.sub.i and delivers and delivers d.sub.c output lists V.sub.i, with i[1 . . . d.sub.c]. Each input list and output list includes n.sub.m elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n.sub.m. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of d.sub.c elements of input lists U.sub.i. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

Embodiments of the invention provide a decoder for determining an estimate of an encoded signal, the decoder comprising one or more variable node processing units (23) and one or more check node processing units (25) configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with said symbol, wherein the decoder comprises: at least one vector permutation unit (24) configured to receive a set of at least three variable node messages comprising variable node components from at least one variable node processing unit and to generate permuted messages depending on a plurality of the reliability metrics comprised in said variable node components, the variable node messages being sorted according to an order of the reliability metrics; and at least one check node processing unit (25-1) configured to: calculate at two or more elementary check node processors (26) a set of syndromes from said at least three permuted messages, generate at least one check node message from said set of syndromes, and send said at least one check node message to a signal estimation unit (29).

Systems and methods for data transport in optical communications systems, including a transmitter for encoding a received information sequence by constructing an outer and inner quasi cyclic-low-density parity check (QC-LDPC) code. The encoding includes dividing the received information sequence into a plurality of messages of equal length, encoding each of the messages into a codeword to generate a plurality of outer codewords, cascading the plurality of outer codewords to generate a bit sequence, and executing inner encoding to encode each of the plurality of outer codewords into codewords in QC-LDPC inner code. A receiver decodes a received data stream based on the QC-LDPC inner code using two-phase decoding including iteratively performing at least one of inner/outer and outer/inner decoding until a threshold condition is reached.