Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all messages except for one message, and combines the hard-decided values with the one message that is not hard-decided, to update a final output message.

A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.

According to one embodiment, a memory system includes: a non-volatile memory; a coding unit that generates a codeword by performing coding of a graph code using a graph of which a side is associated with a block, the block being a part of user data and having one or more symbols at which component codes intersect one another; and a control unit that stores the codeword in the non-volatile memory.

Disclosed is a multi-element code modulation mapping method and device, relating to communications and designed to improve communication reliability. The method includes that: multi-element domain coding is performed on a first sequence including K multi-element codes to obtain a second sequence including N multi-element codes; K.sub.1 and K.sub.2 are calculated according to a multi-element domain element number q and a modulation order M, wherein K.sub.1*log.sub.2 q=K.sub.2*log.sub.2 M, both K.sub.1 and K.sub.2 are integers not smaller than 2, and both q and M are power of 2; the second sequence is divided into z groups of multi-element codes with each group including K.sub.1 multi-element codes, wherein C=formula (I), and formula (II) represents rounding up; each group of multi-element codes is mapped to a constellation diagram to form K.sub.2 Mth-order modulation symbols; and z groups of Mth-order modulation symbols are sequentially cascaded to form a modulation symbol to be sent. The present disclosure further discloses a computer storage medium.

An extension to the enhanced serial generalized bit-flipping decoding algorithm (ES-GBFDA) of non-binary LDPC codes by introducing soft information in the check node operation. The application not only considers the most reliable symbol in the syndrome computation, but also takes at least the second most reliable symbol of each incoming message into account. An extended information set is available for the parity-check node update and this allows introducing the concept of weak and strong votes performed by the check node unit. Each variable node can receive two kinds of votes, whose amplitudes can be tuned to the reliability of the syndrome that produces the vote.

A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits.