A method and a device of selecting a base graph of a low-density parity-check code are provided. The method includes: acquiring a data information length and a channel coding rate of to-be-encoded data; determining a target base graph selection strategy according to the data information length and an information length range of a base graph; determining a target base graph for the to-be-encoded data according to the target base graph selection strategy and the channel coding rate.

Examples relate to apparatuses, devices, methods, and computer programs for generating and employing LDPC (low-density parity-check code) matrices, and to communication devices, memory devices or storage devices comprising such apparatuses or devices. An apparatus for generating an LDPC matrix comprises processing circuitry. The processing circuitry is configured to generate the LDPC matrix using a generator algorithm. The LDPC matrix is generated for codewords with one or more punctured or erased bits. The LDPC matrix is generated observing one or more constraints. For example, the one or more constraints may comprise one or more of the following: a) for each column corresponding to a punctured or erased bit, the LDPC matrix comprises a row comprising a 1 in the column and a 0 in the other columns corresponding to a punctured or erased bit, b) in a row for a given check node, at most two is are present in columns corresponding to punctured or erased bits, and c) each column corresponding to a punctured or erased bit has a column weight of at least 7 and at most 35.

A method for supporting a rate-compatible non-binary LDPC code, performed by a wireless device, according to the present embodiment, comprises the steps of: acquiring a kernel part comprising a plurality of first check nodes and a plurality of first variable nodes, the kernel part having a predetermined first code rate applied thereto, and the level of each of the plurality of first variable nodes included in the kernel part being set to 2; and generating, on the basis of the kernel part, a protograph having a second code rate, when a change from the first code rate to the second code rate is required.

Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).

Encoding bits with a Q-ary linear error correction code defined over a binary-extension Galois field GF(2k), defined by a quasi-cyclic parity-check matrix comprising: first, second and third circulant sub-matrices comprising respective circulants respectively having first, second and third shifts and defined by first, second and third parameters belonging to the Galois field GF(2k), the second shift equal to a difference between a number of rows of each circulant and the first shift. A first set of parity-check bits is determined according to a fourth circulant having a shift equal to a difference between the number of rows and the first and third shifts and defined by the multiplicative inverse of a product between the first and third parameters, and to the second and third circulant sub-matrices. A second set of parity-check bits is determined according to the first set of parity-check bits and the first and second circulant sub-matrices.

This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A method for supporting a rate-compatible non-binary LDPC code, performed by a wireless device, according to the present embodiment, comprises the steps of: acquiring a kernel part comprising a plurality of first check nodes and a plurality of first variable nodes, the kernel part having a predetermined first code rate applied thereto, and the level of each of the plurality of first variable nodes included in the kernel part being set to 2; and generating, on the basis of the kernel part, a protograph having a second code rate, when a change from the first code rate to the second code rate is required.

The present technology relates to an electronic device. More specifically, the present technology relates to a memory controller and a method of operating the same. According to an embodiment, a memory controller includes an error corrector configured to receive read data from a memory device and output a first message obtained by performing error correction decoding on the read data based on a parity check matrix, a randomizer configured to generate a second message by inverting the first message, and an operation controller configured to output the second message, wherein the parity check matrix is a matrix in which a number of elements, each of which is one (1) among elements included in each row, is an even number or a matrix in which an exclusive OR on elements included in each row is zero (0).

Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.

The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.