H03M13/1174

GENERALIZED LOW-DENSITY PARITY CHECK CODES IN DIGITAL COMMUNICATION SYSTEM

Provided is an encoder, a decoder, a computer-readable medium and methods of forward error correction channel encoding/decoding within a HARQ scheme, based on a generalized quasi-cyclic low-density parity-check code comprising a Cordaro-Wagner component code.

Permutation network designing method, and permutation circuit of QC-LDPC decoder

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises MN sub-matrices, wherein each of the sub-matrices is a ZZ matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes

Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.

Permutation network designing method, and permutation circuit of QC-LDPC decoder

A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises MN sub-matrices, wherein each of the sub-matrices is a ZZ matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.

Storage drive error-correcting code-assisted scrubbing for dynamic random-access memory retention time handling
10691532 · 2020-06-23 · ·

Systems, devices, and methods for providing ECC-assisted scrubbing of memory devices and error correction of memory devices. In one embodiment, a method is disclosed comprising obtaining, at a storage device, data and a first parity portion to write to a memory device, the first parity portion generated via a first encoding; encoding, at the storage device, the data with a second encoding to generate a second parity portion; aligning, by the storage device, the data, the first parity portion, and the second parity portion according to a predefined alignment scheme, the aligning generating aligned data; and writing, by the storage device, the aligned data to the memory device.

Data processing device and data processing method

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

MULTIPLE INCREMENTAL REDUNDANCY SCHEME USING LINEAR RATELESS CODES
20240022350 · 2024-01-18 ·

Methods, systems, and devices for wireless communications are described. In some examples, a first device may combine, for each of a set of sub-blocks of a block of data, a set of unencoded bits associated with a respective sub-block with a matrix to generate a set of encoded bits. The first device may transmit a first message including the block to a second device. The second device may determine respective probabilities of successful decoding of respective selected candidate codewords for the set of sub-blocks of the block based on receiving the first message and may transmit one or more indicators associated with one or more sub-blocks based on the respective probabilities of successful decoding of the respective selected candidate codewords. The first device may transmit a second message including redundancy information for the one or more sub-blocks based on transmitting the one or more indicators

GENERALIZED LOW-DENSITY PARITY CHECK CODES (GLDPC)

Provided is a system and method for determining a generalized LDPC code for forward error correction channel coding that has a repeat-accumulate code structure.

Repetition Scheme for Flexible Bandwidth Utilization
20200153550 · 2020-05-14 ·

A network device implements a repetition scheme to generate a repetition-encoded forward error correction (FEC) codeword for a FEC codeword. The repetition-encoded FEC codeword includes a set of N offset-shifted bit sequences. In some embodiments, each bit sequence is formed by M replicas of the FEC codeword and an offset is applied to shift the bit sequence where the offset is different for each bit sequence. The set of N offset-shifted bit sequences are allocated into N orthogonal frequency-division multiplexing (OFDM) symbols, wherein each offset-shifted bit sequence is allocated over a corresponding OFDM symbol.

ELECTRONIC DEVICE FOR PERFORMING CODE-BASED ENCRYPTION SUPPORTING INTEGRITY VERIFICATION OF A MESSAGE AND OPERATING METHOD THEREOF

Disclosed is an electronic device for performing code-based encryption supporting integrity verification of a message and an operating method thereof. When a data transmission side encrypts a message through code-based encryption and transmits the encrypted message to a data reception apparatus, the data transmission side is allowed to use a hash value generated based on a part of the message as an error in code-based encryption to support the data reception apparatus to verify an integrity of a received message by using the hash value.