Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector c=ū.Math.G, wherein G is a K×N generator matrix derived from a parity check matrix H.sub.l; and wherein H.sub.l is derived from a base parity check matrix H by summing different rows in the base parity check matrix H to obtain an intermediate parity check matrix, and applying a lifting matrix to the intermediate base parity check matrix to obtain H.sub.l.

The present disclosure provides a method for optimizing a protograph-based LDPC code over an underwater acoustic (UAW) channel. The traditional protograph-based LDPC code over an UAW channel does not consider performance in an error floor region. The method first determines parameters such as a protograph-based LDPC code length, a basic protograph, a target decoding threshold, a threshold adjustment factor, and an ACE check parameter. The protograph is optimized, and the method constructs a parity check matrix by using a UAW channel-based PEG/ACE hybrid algorithm, performs ACE check on the parity check matrix, and calculates a decoding threshold for the matrix passing the check. If the decoding threshold is within a range of an iterative decoding threshold, the parity check matrix is a final optimized matrix. Otherwise, the method continues to optimize the protograph until a parity check matrix passing the check is obtained.

Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.

An integrated circuit (IC) device is disclosed. The IC device includes an error encoder to receive a word of k bits and to encode the word using a G-matrix to generate an encoded word of n bits. The n bits include the k bits and n-k check bits. The G matrix is based on a parity check matrix defining a single error correct, double error detect, and burst error detect (SECDEDBED) code. An error decoder receives the encoded word and applies the parity check matrix to the encoded word. The parity check matrix is configured to generate a syndrome from the encoded word. The syndrome being used to detect a random double bit error, a random single bit error, and a burst error of between two and m bits within m adjacent bits of an m-bit subset of the data word starting from an m-bit boundary of the word of k bits, and where m <n-k.

In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A,114B), LDPC encoded data formed by LDPC encoding blocks (102A,102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).

A method in a node (110, 115) comprises generating (604) a plurality of constituent polar codes, each of the plurality of constituent polar codes having an associated block length and an associated set of information bits. The method comprises coupling (608) at least a portion of the sets of information bits associated with each of the plurality of constituent polar codes to generate a spatially coupled polar code. The method comprises encoding (612) a wireless transmission using the spatially coupled polar code.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

A fault-tolerant analog computing device includes a crossbar array having a number l rows and a number n columns intersecting the l rows to form l×n memory locations. The l rows of the crossbar array receive an input signal as a vector of length l. The n columns output an output signal as a vector of length n that is a dot product of the input signal and the matrix values defined in the l×n memory locations. Each memory location is programmed with a matrix value. A first set of k columns of the n columns is programmed with continuous analog target matrix values with which the input signal is to be multiplied, where k<n. A second set of m columns of the n columns is programmed with continuous analog matrix values for detecting an error in the output signal that exceeds a threshold error value, where m<n.

Disclosed is an electronic device for performing code-based encryption supporting integrity verification of a message and an operating method thereof. When a data transmission side encrypts a message through code-based encryption and transmits the encrypted message to a data reception apparatus, the data transmission side is allowed to use a hash value generated based on a part of the message as an error in code-based encryption to support the data reception apparatus to verify an integrity of a received message by using the hash value.

A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.