Patent classifications
H03M13/1177
Communication method and communications apparatus
Embodiments of this application disclose a communication method and a communications apparatus. The method includes: determining an encoding matrix type of a first sequence based on a modulation and encoding scheme (MCS) index, where the first sequence is obtained after code block segmentation is performed on a second sequence, a length of the second sequence is related to the MCS index, and a length of the first sequence is less than or equal to a first threshold; and encoding the first sequence based on the encoding matrix associated with the encoding matrix type. According to the application, the encoding matrix type can be properly selected for encoding.
Transmission method and reception method
In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A,114B), LDPC encoded data formed by LDPC encoding blocks (102A,102B). In a case of a retransmittal, the multi-antenna transmitting apparatus (100) uses a transmission method, in which the diversity gain is higher than in the previous transmission, to transmit only a part of the LDPC encoded data as previously transmitted. For example, the only the part of the LDPC encoded data to be re-transmitted is transmitted from the single antenna (114A).
Load Balanced Decoder Systems And Methods
A decoding circuit system includes a load balancing scheduler circuit, a full range decoder circuit, and an auxiliary decoder circuit. The load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit. The full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data. The load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the auxiliary decoder circuit. The auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data.
Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells
Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
Low density parity check decoder
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes LDPC decoding circuitry comprising a Q message generator and a P sum adder array. The Q message generator combines an R message from a previous iteration with a P message to produce a Q message. The P sum adder array adds the P message to a difference of an R message from a current iteration and the R message from the previous iteration to produce an updated P message.
TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.
METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM
A channel encoding method in a communication or broadcasting system is provided. The channel encoding method includes reading a first sequence corresponding to a parity check matrix, converting the first sequence to a second sequence by applying a certain rule to a block size corresponding to a parity check matrix and the first sequence, and encoding information bits based on the second sequence. The block size has at least two different integer values.
ANALOG ERROR DETECTION AND CORRECTION IN ANALOG IN-MEMORY CROSSBARS
An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other nonvolatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.
METHOD AND APPARATUS FOR DECODING DATA PACKETS IN COMMUNICATION NETWORK
The present disclosure relates to a method and an apparatus for decoding data packets in communication network. The method comprises receiving one or more data packets related to each of one or more data types; and decoding the one or more data packets using a parity check matrix associated with the corresponding data type, wherein the parity check matrix comprises a plurality of layers, arranged according to a combination of layers which is determined using a reinforcement model.