An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.

Methods and systems for providing a virtual HDBaseT link. In one embodiment, a first switch transmits packets over an Ethernet network that includes one or more hops. The payload of each of the packets includes an HDBaseT T-packet belonging to an HDBaseT session. A first processor sets, for each packet from among a plurality of the packets, a timestamp value in the packet to correspond to the time at which the packet is transmitted by the first switch. A second switch receives the packets over the Ethernet network. A second processor calculates a clock correction value based on the timestamps in the plurality of packets, and utilizes the clock correction value to perform at least one of the following: (i) control transmission, by the second switch, of data in T-packets in the payloads of the packets, and (ii) recover a source clock of native media delivered over the Ethernet network.

Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrix associated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row having two elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same column as the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.

A low-density parity-check (LDPC) code encoding method and a communication apparatus are described that provide increased redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. A check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.

Decoding method and memory system that decodes data and estimates a weighted checksum on the decoded data to determine whether the decoding is successful. The weighted checksum is calculated based on a first group and a second group, the first group is associated with weights for high degree nodes of an irregular parity check matrix, and the second group is associated with weights for low degree nodes of the irregular parity check matrix.

The disclosure discloses a method for supporting low bit rate coding. A source data packet to be coded is repeated for i times, and the data packet which is repeated for i times is coded. The disclosure also discloses an apparatus for supporting low bit rate coding and a computer storage medium.

Methods and systems for enabling recovery of lost packets transmitted over a communication network. In one embodiment, a device includes a processor and a transmitter. The processor is configured to calculate a row parity packet (RPP) and a diagonal parity packet (DPP) for n packets. Each of the RPP, the DPP, and the n packets comprises n segments. The processor utilizes each packet, from among the n packets, to update parity values in the RPP and the DPP in such a way that each segment in the packet is used to update one segment in the RPP and at most one segment in DPP. The transmitter transmits the n packets, the RPP, and the DPP over the communication network. Receiving a subset of n members of a set comprising: the RPP, the DPP, and the n packets, enables recovery of two lost packets.

A low-density parity check convolution code (LDPC-CC) is made, and a signal sequence is sent after being subjected to an error-correcting encodement using the low-density parity check convolution code. In this case, a low-density parity check code of a time-variant period (3g) is created by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

A LDPC decoder includes: a coded information receiving circuit, configured to receive coded information and initialize bit information of a variable node; a check node processing circuit, configured to receive first reliability information, and perform check node processing and output second reliability information; a variable node processing circuit, configured to receive the second reliability information, and perform variable node processing to update the bit information of the variable node; a decoding decision circuit, configured to perform a decoding decision for the bit information of the variable node; and a scaling circuit configured to scale the first reliability information transmitted, the second reliability information and the bit information of the variable node.

Methods and systems that enable recovery lost packets that were transmitted over a communication network. In one embodiment, a device includes a receiver and a processor. The receiver receives n packets that belong to a set comprising n+2 packets transmitted over the communication network, where the set includes: n data packets, a row parity packet (RPP), and a diagonal parity packet (DPP). Each received packet comprises n segments. Each segment of the RPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet from among the n data packets. Each segment of the DPP comprises a result of a parity function applied to a set comprising n segments, each belonging to a different packet selected from a group comprising the n data packets and the RPP. The processor may utilize the received packets to recover two lost packets.