An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.

Methods and Apparatus for processing data encoded by low density parity check (LDPC) in a communication system are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: encoding an information bit sequence based on an LDPC coding scheme to obtain an encoded bit sequence; generating a master bit sequence based on the encoded bit sequence; selecting a subset of the master bit sequence according to a rate matching rule to obtain a rate matched bit sequence; interleaving the rate matched bit sequence according to a predetermined index sequence to obtain a to-be-transmitted bit sequence; and transmitting the to-be-transmitted bit sequence to a second node.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.

A sending device may obtain a first to-be-encoded vector. The sending device may perform first encoding on the first to-be-encoded vector, to obtain a second to-be-encoded vector. The sending device may encode the second to-be-encoded vector based on a first generator matrix, to obtain an encoded codeword. The first generator matrix may include at least N+1 submatrices a, and N of the submatrices a may be located on a main diagonal of the first generator matrix. The first generator matrix may be a block upper triangular matrix, or the first generator matrix may be a block lower triangular matrix. The submatrix a is a polar kernel matrix with a size of 2.sup.m*2.sup.m, m is a natural number, and N is a natural number. The sending device may send the encoded codeword.

The present disclosure relates generally to the field of data encoding and decoding, and particularly to automorphism-based polar encoding and decoding apparatuses and methods, as well as computer program products embodying the method steps in the form of computer codes. More specifically, polar codes are designed such that their frozen bits support automorphisms described by a binary upper triangular matrix having a diagonal including at least one of zeros and units. Codewords generated using these polar codes may be subsequently subjected to automorphism-based polar decoding in an efficient manner and with a lower decoding latency compared to the conventional Successive Cancellation List decoding algorithms. Furthermore, the efficiency of the automorphism-based polar decoding may be increased even more if the automorphisms are based on matrix elements arranged above the diagonal in a vicinity of a bottom right corner of the binary upper triangular matrix.

Encoding bits with a Q-ary linear error correction code defined over a binary-extension Galois field GF(2k), defined by a quasi-cyclic parity-check matrix comprising: first, second and third circulant sub-matrices comprising respective circulants respectively having first, second and third shifts and defined by first, second and third parameters belonging to the Galois field GF(2k), the second shift equal to a difference between a number of rows of each circulant and the first shift. A first set of parity-check bits is determined according to a fourth circulant having a shift equal to a difference between the number of rows and the first and third shifts and defined by the multiplicative inverse of a product between the first and third parameters, and to the second and third circulant sub-matrices. A second set of parity-check bits is determined according to the first set of parity-check bits and the first and second circulant sub-matrices.

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. LDPC coding for information bits with an information length K=N×r is performed on the basis of an extended parity check matrix having rows and columns extended by a predetermined puncture length L with respect to a parity check matrix of an LDPC code with a code length N of 69120 bits and a coding rate r of 14/16, so that an extended LDPC code having parity bits with a parity length M=N+L−K is generated. A head of the information bits of the extended LDPC code is punctured by L, so that a punctured LDPC code with the code length N of 69120 bits and the coding rate r is generated. The extended parity check matrix includes an A matrix of M1 rows and K columns expressed by a predetermined value M1 and the information length K=N×r, a B matrix of M1 rows and M1 columns, a Z matrix of M1 rows and N+L−K−M1 columns, a C matrix of N+L−K−M1 rows and K+M1 columns, and a D matrix of N+L−K−M1 rows and N+L−K−M1 columns. The present technology can be applied to data transmission and the like using an LDPC code.

A media content-based adaptive method, device and system for Forward Error Correction (FEC) coding and decoding of a systematic code, and a medium are provided. The method includes: dividing, according to the importance of media content, source data into N types of source data packets according to priorities; generating N types of intermediate codes according to the N types of source data packets and the priorities thereof; setting, according to the N types of intermediate codes, recovery data of N types of source data according to a channel condition, and generating coded symbols of N types of systematic codes; receiving the coded symbols, and arranging and sorting the coded symbols according to decoding requirements; and decoding, according to the number of received coded symbols, intermediate codewords according to different situations, and recovering the corresponding source data packets according to the intermediate codewords.