The present technology relates to a data processing apparatus and a data processing method that are able to provide an LDPC code with a good error rate. An LDPC encoder performs coding by an LDPC code having a code length of 16200 bits and a code rate of 12/15. The LDPC code includes an information bit and a parity bit, and a parity check matrix H is configured with an information matrix portion corresponding to the information bit of the LDPC code and a parity matrix portion corresponding to the parity bit. An information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table representing a position of an element of 1 in the information matrix portion at an interval of 360 columns. The present technology may be applied to a case of performing an LDPC coding and an LDPC decoding.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, 6/15, or 8/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, 6/15, or 8/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

The present invention discloses an erasure code calculation method, including the following steps: S1) splitting original data, and building an original encoding matrix M; S2) acquiring a transverse exclusive OR encoding matrix M1; S3) acquiring a longitudinal exclusive OR encoding matrix M2; S4) acquiring an exclusive OR encoding matrix M3 according to the transverse exclusive OR encoding matrix M1 and the longitudinal exclusive OR encoding matrix M2; S5) transforming a data position of the transverse exclusive OR encoding matrix M1 to acquire a storage matrix M4; S6) judging whether storage nodes at which the last column of data of the storage matrix M4 is stored are damaged; S7) restoring the lost data according to a position 1 of the damaged node; and S8) restoring the lost data according to a position 2 of the damaged node. In the present invention, the operation is rapid, and calculation efficiency is high.

A memory controller is provided to include an error correction encoder and an error correction decoder. The error correction encoder is configured to encode a message at a second code rate and generate a codeword including a message part, a first parity part, and a second parity part. The error correction decoder is in communication with the error correction encoder and configured to perform at least one of i) first error correction decoding operation at a first code rate greater than the second code rate based on a first parity check matrix and first read values or ii) second error correction decoding operation at the second code rate based on a second parity check matrix and second read values. The first read values correspond to a partial codeword including the message part and the first parity part, and the second read values correspond to an entire codeword.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit strings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

A method for performing encoding on the basis of a parity check matrix of a low density parity check code according to the present embodiment comprises the steps of: generating a parity check matrix by a terminal, wherein the parity check matrix corresponds to a characteristic matrix, each component of the characteristic matrix corresponds to a shift index value determined through a modulo operation between a corresponding component in a basic matrix and Zc, which is a lifting value, and the basic matrix is a 42×52 matrix; and performing encoding of input data, by the terminal, using the parity check matrix, wherein the lifting value is associated with the length of the input data.

A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.