A decoder includes a syndrome calculator, a Key Equation Solver (KES) and an error corrector. The syndrome calculator is configured to receive an n-symbol code word encoded using a Reed Solomon (RS) code to include (nk) redundancy symbols, and to calculate for the code word 2t syndromes Si, t=(nk)/2 is a maximal number of correctable erroneous symbols. The KES is configured to derive an error locator polynomial (x) whose roots identify locations of erroneous symbols, by applying to the syndromes a number of t iterations. In a single iteration of the t iterations the NES is configured to calculate two discrepancies between (x) and respective two candidates of (x), and to derive from the two candidates an updated candidate of (x). The error corrector is configured to recover the code word by correcting the erroneous symbols using the derived error locator polynomial (x).

A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.

Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.

A method includes, storing a set of valid codewords including: a first valid functional codeword representing a functional state of a controller subsystem; a first valid fault codeword representing a fault state of the controller subsystem and characterized by a minimum hamming distance from the first valid functional codeword; a second valid functional codeword representing a functional state of a controller; and a second valid fault codeword representing a fault state of the controller; in response to detecting functional operation of the controller subsystem, storing the first valid functional codeword in a first memory; in response to detecting a match between contents of the first memory and the first valid functional codeword, outputting the second valid functional codeword; in response to detecting a mismatch between contents of the first memory and every codeword in the first set of valid codewords, outputting the second valid fault codeword.

A method of operation for a Reed-Solomon decoder includes receiving partial input data of symbols of a Reed-Solomon codeword; updating Reed-Solomon syndromes and error location polynomial coefficients based on the partial input data; maintaining the Reed-Solomon syndromes and the error location polynomial coefficients in a memory prior to starting activation of Reed-Solomon decoding; and inputting the Reed-Solomon syndromes and the error location polynomial coefficients to a first activation of Reed-Solomon decoding including calculating an initial error evaluator polynomial as a first error evaluator polynomial, performing error detection based on the first error evaluator polynomial to determine presence and location of errors in an input Reed-Solomon codeword, and updating the error location polynomial when errors are found in the input Reed-Solomon codeword. The error location polynomial coefficients in the memory are updated during each activation of Reed-Solomon decoding when at least one error is identified in the Reed-Solomon codeword.

An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

A construction method for a (n,n(n1),n1) permutation group code based on coset partition is provided. The presented (n,n(n1),n1) permutation group code has an error-correcting capability of d1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n1 and a code set size of n(n1), the invention provides a method of calculating n1 orbit leader permutation codewords by O.sub.n={o.sub.1}.sub.=1.sup.n1(mod n) and enumerating residual codewords of the code set by P.sub.n=C.sub.nO.sub.n={(l.sub.1).sup.n1O.sub.n}={(r.sub.n).sup.n1O.sub.n)}. Besides, a generator of the code set thereof is provided. The (n,n(n1),n1) permutation group code of the invention is an algebraic-structured code, n1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers. Composition operations of the cyclic subgroup C.sub.n acting on all permutations o.sub. of the orbit leader permutation array O.sub.n are replaced by well-defined cyclic shift composite operation functions (l.sub.1).sup.n1 and (r.sub.n).sup.n1 so that the action of the cyclic group acting on permutations is realized by a group of cyclic shift registers.

A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.

Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.

A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with respect to a linear code. A difference between the syndromes of the first and second messages is calculated, and a vector that minimizes a metric in a coset defined by the syndrome difference is identified. A compact representation of the second message that is based upon the first message is generated when a metric of the identified vector is less than or equal to a predetermined threshold. The compact representation of the second message is stored in a location of a memory device assigned for storing the second message, when the metric of the identified vector is less than or equal to the predetermined threshold.