The present disclosure relates to methods and systems for decoding a Bose-Chaudhuri-Hocquenghem (BCH) encoded codeword. The methods may include receiving a codeword over a data channel; determining a plurality of syndrome values for the codeword during a first time interval; determining a set of initial elements during the first time interval; generating an error locator polynomial based on the plurality of syndrome values, the error locator polynomial representing one or more errors in the codeword; evaluating, based on the set of initial elements, the error locator polynomial to identify one or more error locations corresponding to the one or more errors in the codeword; and correcting the codeword based on the one or more error locations.

A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.

A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.

A decoder includes a syndrome calculator, a Key Equation Solver (KES) and an error corrector. The syndrome calculator receives an n-symbol code word encoded using a Reed Solomon (RS) code to include (nk) redundancy symbols, calculates for the code word 2t syndromes Si, t=(nk)/2 is a maximal number of correctable erroneous symbols. The KES derives an error locator polynomial {circumflex over ()}(x) whose roots identify locations of erroneous symbols, by applying to the syndromes a number of t iterations. In each iteration the KES calculates two discrepancies between {circumflex over ()}(x) and respective two candidates of {circumflex over ()}(x), and derives from the two candidates an updated candidate of {circumflex over ()}(x). The error corrector recovers the code word by correcting the erroneous symbols using the derived error locator polynomial {circumflex over ()}(x).

A Reed Solomon decoder may include a syndrome calculation (SC) circuit configured to calculate a codeword from a syndrome ; a key equation solver (KES) circuit configured to calculate an error location polynomial and an error evaluation polynomial from the syndrome; and a Chien search and error evaluation (CSEE) circuit configured to calculate an error location and an error value from the error location polynomial and the error evaluation polynomial, wherein the KES circuit comprises a plurality of sub-KES circuit and each of the plurality of sub-KES circuit, the SC circuit and the CSEE circuit constitutes pipeline stages respectively.

Embodiments of the present disclosure provide a high speed low latency rate configurable soft decision and hard decision based pipelined Reed-Solomon (RS) decoder architecture suitable for optical communication and storage. The proposed RS decoder is a configurable RS decoder that is configured to monitor the channel and adjust code parameters based on channel capacity. The proposed RS decoder includes interpolation and factorization free Low-Complexity-Chase (LCC) decoding to implement soft-decision decoder (SDD). The proposed RS decoder generates test vectors and feeds these to a pipelined 2-stage hard decision decoder (HDD). The proposed RS decoder architecture computes error locator polynomial in exactly 2t clock cycles without parallelism and supports high throughput, and further computes error evaluator polynomial in exactly t cycles. The present disclosure provides a 2-stage pipelined decoder to operate at least latency possible and reduced size of delay buffer.