The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

A memory system includes a non-volatile memory and a memory controller. The memory stores data encoded with an error correction code for correcting errors of n (n is 3 or more) bits or less. The controller estimates the number of error bits by using syndromes calculated from a received word. When the number of error bits is two or three, the controller executes variable transformation on a variable of an error locator polynomial corresponding to the number of error bits with a first value or a second value based on the syndromes. The controller also executes, with the first/second values, calculation of roots of a transformed polynomial obtained by converting the error locator polynomial. The controller obtains roots of the error locator polynomial by variable inverse transformation on the roots of the transformed polynomial and corrects the error of the error locations corresponding to the obtained roots.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

A method for decoding a (n, k, d) cyclic code is disclosed. The method includes: receiving a word corresponding to the cyclic code; constructing a look-up table, wherein the look-up table includes k syndrome vectors and k error patterns; computing a syndrome vector of the received word by a hardware processor; comparing the weight of the syndrome vector of the received word with an error-correcting capacity; decoding the received word by adding the received word and the syndrome vector if the weight of the syndrome vector of the received word is not more than the error-correcting capacity; decoding the received word by inverting bits in the message section in sequence and re-compute a syndrome vector of the inverted received word if the weight of the syndrome vector of the received word is more than the error-correcting capacity.

A method for decoding a cyclic code is disclosed. The method includes: determining a plurality of syndromes for the cyclic code; determining, by a hardware processor, a first coefficient and a second coefficient based on the plurality of syndromes; determining, by the hardware processor, a third coefficient based on the second coefficient; and generating an error-locator polynomial based on the first coefficient, the second coefficient, and the third coefficient.

A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2.sup.m1) bits at maximum which is represented by a Galois field GF(2.sup.m), and performs syndrome calculation so as to meet
s.sup.i+.sup.j
z(.sup.i+).sup.1+.sup.1+(.sup.j+).sup.1+.sup.1(A)
thereby calculating syndromes s and z. An error position polynomial coefficient calculation circuit calculates the coefficient of an error position polynomial to obtain sz by multiplying s and z by one multiplier. After that, 2-bit error data positions i and j are specified. Errors at the error data positions i and j of the input data are corrected.

An application specific integrated circuit (ASIC) tangibly encodes a method for fast polynomial updates in fast Chase decoding of binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The method includes the steps of using outputs of a syndrome-based hard-decision (HD) algorithm to find a Groebner basis for a solution module of a modified key equation, upon failure of HD decoding of a BCH codeword received by the ASIC from a communication channel; evaluating polynomials obtained from said Groebner basis at inverses of specified weak-bit locations; and transforming a Groebner basis for a set of flipped weak-bit locations (.sub.1, . . . , .sub.r1) to a Groebner basis for (.sub.1, . . . , .sub.r), wherein .sub.r is a next weak-bit location, wherein r is a difference between a number of errors and a HD correction radius of the BCH codeword.

Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage.

An electronic device for finding error locations in a codeword includes a plurality of power control units configured to find error locations in the codeword. The plurality of power control units are coupled in parallel. Each of the plurality of power control units includes a plurality of corresponding input control circuits to individually turn on or off the corresponding power control unit.