Patent classifications
H03M13/155
Method and decoder for determining an error vector for a data word according to a Reed-Muller code
A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.
ENCODING METHOD, DECODING METHOD, AND APPARATUS
This application discloses an encoding method, a decoding method, and an apparatus. The encoding method includes: obtaining a first bit sequence and a target code length M; then performing first channel encoding on the first bit sequence, to obtain a second bit sequence; performing second channel encoding based on the second bit sequence, to obtain a third bit sequence; and outputting the third bit sequence. The first bit sequence includes K information bits, the second bit sequence includes N bits, and the third bit sequence includes the N bits and E check bits, where M>N, and E=M?N. M, K, N, and E are all integers greater than or equal to 1.
Apparatus and method for correcting at least one bit error within a coded bit sequence
An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.
Device and method for decoding polar code in communication system
The present disclosure relates to a 5.sup.th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a post-4.sup.th generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure is for decoding a polar code in a communication system. An operation method of a reception device comprises the steps of: receiving data encoded by means of a polar code and comprising a plurality of bits; confirming one or more bits which do not require a decoding operation among the plurality of bits; and decoding at least some of the bits remaining after excluding the one or more bits.
METHOD AND APPARATUS FOR PROCESSING DATA
A method for performing polar coding is disclosed in the application. A data block is segmented into a plurality of first blocks. Difference in bit length between any two first blocks is not more than one bit. For each first block, one or more consecutive padding bits is added to obtain a second block of a bit length K if the bit length of the first block is less than K, so as to obtain a plurality of second blocks corresponding to the first blocks. N-K consecutive bits are added to each of the second blocks to obtain a plurality of third blocks. Polar encoding is performed on the third blocks.
Constant hamming weight coding
Encoding or decoding can operate a processing system to apply one or more recursive relations to a known parameter associated with a length m and a Hamming weight l to produce a computed parameter associated with length m1. An encoding process can thus assign values to bits of a code based on comparison of the data value being encoded and the computed parameter. A decoding process can use the computed parameters in a calculation of a decoded data value.
MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD
A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets r.sub.m (r.sub.m is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the r.sub.m) symbols of the r.sub.m symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.
Error correction processing circuit in memory and error correction processing method
A method for correcting error in a memory comprises setting a protected scope for at least part of unit data to be written in the memory according to an operation voltage of the memory; implementing error correction encoding for protected data corresponding to the protected scope among the unit data; and writing the unit data in the memory while matching them with parity data generated as a result of the error correction encoding.
METHOD AND DECODER TO ADJUST AN ERROR LOCATOR POLYNOMIAL BASED ON AN ERROR PARITY
A method of operation of a decoder includes receiving first data at the decoder. The method further includes generating second data at the decoder based on the first data. The second data is generated by adjusting an error locator polynomial based on an error parity of the first data.
Method and apparatus for processing data
A method for performing polar coding is disclosed in the application. A data block is segmented into a plurality of first blocks. Difference in bit length between any two first blocks is not more than one bit. For each first block, one or more consecutive padding bits is added to obtain a second block of a bit length K if the bit length of the first block is less than K, so as to obtain a plurality of second blocks corresponding to the first blocks. NK consecutive bits are added to each of the second blocks to obtain a plurality of third blocks. Polar encoding is performed on the third blocks.