A decoding method includes inputting coded data, and decoding the coded data to obtain decoded data. The coded data are generated by using an encoding process at an encoding apparatus, and the encoding process includes: (i) repeatedly-selecting and collecting first packets included in the decoded data to generate at least one second packet; (ii) dividing at least one third packet included in the decoded data into fourth packets; and (iii) allocating fifth packets included in the decoded data to respective sixth packets without collecting the first packets or dividing the at least one third packet, and performing an error correcting encoding on the at least one second packet, the fourth packets, and the sixth packets in accordance with a coding rate selected from a plurality of coding rates to generate parity data.

A method of performing division operations in an error correction code includes the steps of receiving an output ω∈F†{0} wherein F=GF(2.sup.r) is a Galois field of 2.sup.r elements, ω=Σ.sub.0≤i≤r−1β.sub.i×α.sup.i wherein α is a fixed primitive element of F, and β.sub.i∈GF(2), wherein K=GF(2.sup.s) is a subfield of F, and {1, α} is a basis of F in a linear subspace of K; choosing a primitive element δ∈K, wherein ω=ω.sub.1+α×ω.sub.2, ω.sub.1=Σ.sub.0≤i≤s−1 γ.sub.i×δ.sup.i∈K, ω.sub.2=Σ.sub.0≤i≤s−1 γ.sub.i+s×δ.sup.i∈K, and γ=[γ.sub.0, . . . , γ.sub.r−1].sup.T∈GF(2).sup.r; accessing a first table with ω.sub.1 to obtain ω.sub.3=ω.sub.1.sup.−1, computing ω.sub.2×ω.sub.3 in field K, accessing a second table with ω.sub.2=ω.sub.3 to obtain (1+α×ω.sub.2×ω.sub.3).sup.−1=ω.sub.4+α×ω.sub.5, wherein ω.sup.−1=(ω.sub.1×(1+α×ω.sub.2×ω.sub.3)).sup.−1=ω.sub.3×(ω.sub.4+α×ω.sub.5)=ω.sub.3×ω.sub.4+α×ω.sub.3×ω.sub.5; and computing products ω.sub.3×ω.sub.4 and ω.sub.3×ω.sub.5 to obtain ω.sup.−1=Σ.sub.0≤i≤s−1θ.sub.i×δ.sup.i+α.Math.Σ.sub.i≤i≤s−1θ.sub.i+s=δ.sup.i where θ.sub.i∈GF(2).

Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.

A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.

An error correction code (ECC) decoder includes a syndrome calculation block and a path controller. The syndrome calculation block is configured to perform a syndrome calculation for generating a syndrome from a codeword. The path controller is configured to output data transmitted through first to third paths. The first path is a path for transmitting the codeword to the path controller when no error is detected. The second path includes a single-error decoding logic circuit, and the single-error decoding logic circuit corrects a single error of the codeword to transmit the corrected codeword to the path controller through the second path. The third path includes a multi-error decoding logic circuit, and the multi-error decoding logic circuit corrects at least two errors of the codeword to transmit the corrected codeword to the path controller.

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

This application provides an encoding method and apparatus in a wireless communications system. The method includes: performing cyclic redundancy check (CRC) encoding on A to-be-encoded information bits based on a CRC polynomial, to obtain a first bit sequence, where the first bit sequence includes L CRC bits and the A information bits; and performing polar encoding on the first bit sequence, where L has a value of one of 3, 4, 5, 8, and 16. Based on an improved CRC polynomial, coding satisfying a false alarm rate (FAR) requirement is implemented.

An error correction and fault tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to 5 disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2×E≤4 are reconstituted. Some combinations of faulty disks wherein Z+2×E≥5 are either reconstituted, or errors are limited to a small list.

A method for correcting an error of a received signal is provided. The method includes: determining a target degree based upon a length of the received signal; obtaining plural primitive polynomials each having a degree equal to the target degree; selecting one of the primitive polynomials as a target polynomial; defining plural syndromes according to the received signal; generating a group of product values based on the syndromes; obtaining plural coefficient polynomials based on the product values; obtaining monomial trace coefficients based on the coefficient polynomials; generating an error correction value based on the monomial trace coefficients; and correcting the error based on the error correction value.

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.