Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first number and the second number. Adders equal in number to the groups add outputs of multipliers in respective ones of the groups. Accumulation circuitry accumulates outputs of the adders. Output circuitry adds outputs of the adders to an output of the accumulation circuitry to provide a syndrome. Selection circuitry directs outputs of the adders to the accumulation circuitry or the output circuitry, and resets the accumulation circuitry.

A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number nk of independent spinors S.sub.r from the first stabilizer C and a first ordered set S.sub.C consists of the independent spinors S.sub.r; choosing a number nk of independent spinors .sub.r from a second stabilizer in the intrinsic coordinate and a second ordered set .sub.r consists of the independent spinors .sub.r consist; implementing an encoding Q.sub.en, wherein the encoding Q.sub.en converts the first ordered set S.sub.C to the second ordered set S.sub., wherein the encoding Q.sub.en is a sequential product provided by sequential operations of a number nk of unitary operators Q.sub.r; wherein each of the unitary operator Q.sub.r is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Q.sub.en converts and maps the r.sup.th independent spinor S.sub.r in the first ordered set S.sub.C to the r.sup.th independent spinor .sub.r in the second ordered set S.sub. correspondingly; a fault tolerant action .Math. in the quantum code [n, k, C] generated by the second stabilizer in the intrinsic coordinate, wherein the fault tolerant action .Math. is a direct sum of a basis state operator and a correction operator ; and acquiring a fault tolerant encode in the quantum code [n, k, C] generated by the first stabilizer C, wherein the fault tolerant encode is a sequential product of the encoding Q.sub.en, the fault tolerant action .Math. and a complex conjugate Q.sub.en.sup. of the encoding Q.sub.en.

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

The present disclosure relates to information transmission method, decoding method, and apparatus. One example method includes encoding, by a sending device, a to-be-encoded sequence based on preset parameters to obtain an encoded sequence, where the preset parameters include a quantity of check bits, positions of the check bits, and a check equation, and sending the encoded sequence to a receiving device.

An error correction and fault, tolerance method and system for an array of disks is presented. The array comprises k+5 disks, where k disks store user data and 5 disks store computed parity. The present invention further comprises a method and a system for reconstituting the original content of each of the k+5 disks, when up to disks have been lost, wherein the number of disks at unknown locations is E and the number of disks wherein the location of the disks is known is Z. All combinations of faulty disks wherein Z+2E4 are reconstituted. Some combinations of faulty disks wherein Z+2E5 are either reconstituted, or errors are limited to a small list.

An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using Equation 1 as a g-th (g=0, 1, . . . , q1) parity check polynomial to satisfy 0.

The current document is directed to component-efficient CRC-code-computation logic used in electronic-communications hardware. Many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. The currently disclosed CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2.sup.m) is represented by ; a lookup table f(.sup.j) for different power exponents of is established, where the value of j is selected from all the integers ranging from 0 to 2m1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(.sup.j).

A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

Bits in a received word that is based on a codeword of a polar code are decoded to generate decoded bits. A lower-order partial sum is updated based on the decoded bits, and a higher-order partial sum based on the lower-order partial sum is computed. The higher-order partial sum computation is a live computation performed during decoding of a subsequent bit in the received word in some embodiments. In decoding the subsequent bit, nodes in a Data Dependency Graph (DDG) of the polar code may be traversed in a reverse order relative to node indices of at least some of the nodes in the DDG. A reverse order may also be applied to partial sum computations, to combine multiple lower-order partial sums that are based on previously decoded bits according to a reverse order relative to an order in which at least some of the previously decoded bits were decoded.