In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using Equation 1 as a g-th (g=0, 1, . . . , q1) parity check polynomial to satisfy 0.

A method for repairing a single erasure in a Reed Solomon code in a system of a plurality of n storage nodes and a controller, wherein a content of each storage node is a codeword and each node stores a vector v. The method includes identifying a failed storage node; transmitting an index of the failed storage node to each surviving storage node; multiplying the content of each node i by a j-th component of a vector that is a permutation of elements of vector v that correspond to the surviving storage nodes; determining a trace map of the result and converting the result from an mr bit representation into a reduced representation of r bits; reconstructing the content of the failed storage node from the reduced representation of each surviving node's content; and outputting the reconstructed content of the failed storage node.

An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

Provided is a CRC calculation circuit capable of dealing with various types of generator polynomials with a simple configuration. A CRC calculation circuit (100) includes a generator polynomial register (110) configured to store polynomial data, and a plurality of CRC calculation units (120) connected in series and provided so as to correspond to the number of bits of input data. The CRC calculation units (120) each include a barrel shifter (121) configured to shift calculated data by one bit using the input data or output data from a pre-stage CRC calculation unit as the calculated data; an XOR circuit (122) configured to perform XOR calculation of the shifted data and the polynomial data; and a multiplexer (123) configured to select, based on the calculated data, the shifted data or calculation result data.

An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N.sub.0, K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (N.sub.j, K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D.sub.0(x) and a remainder R.sub.0(x) of x.sup.N.sub.0.sup.Km(x) relative to g.sub.0(x). An (h+1).sup.th incremental encoding unit is configured to obtain, according to a quotient D.sub.h(x) and a remainder R.sub.h(x), a quotient D.sub.h+1(x) and a remainder R.sub.h+1(x) of x.sup.N.sub.h+1.sup.Km(x) relative to g.sub.h+1(x).

A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using Equation 1 as a g-th (g=0, 1, . . . , q1) parity check polynomial to satisfy 0.

The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance, including an encoder configured to compute parity data based, at least in part, on program data and on predetermined coefficient data. The predetermined coefficient data is determined independent of the program data.

An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.