A method for error correction in a quantum computing device that can significantly improve the quantum error correcting performance of subsystem codes. By changing the order in which check operators are measured, valuable additional information can be gained. A method for decoding which uses this information to improve performance is also provided.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

A method includes receiving, by a MMU for a processor core, an address translation request from the processor core and providing the address translation request to a TLB of the MMU; generating, by matching logic of the TLB, an address transaction that indicates whether a virtual address specified by the address translation request hits the TLB; providing the address transaction to a general purpose transaction buffer; and receiving, by the MMU, an address invalidation request from the processor core and providing the address invalidation request to the TLB. The method also includes, responsive to a virtual address specified by the address invalidation request hitting the TLB, generating, by the matching logic, an invalidation match transaction and providing the invalidation match transaction to one of the general purpose transaction buffer or a dedicated invalidation buffer.

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

Exemplary methods, apparatuses, and systems include receiving a request for a segment of data. The requested segment data is one of a plurality of segments of data in a stripe of data. A failure to decode the requested segment is detected. Each of the plurality of segments in the stripe other than the requested segment are read. Reading each segment includes reading raw encoded data and attempting to decode the raw encoded data, the result of reading each segment including decoded data when decoding is successful and the raw encoded data when decoding fails. A combined result of each read is generated. The combining includes combining decoded data for segments that were successfully decoded and the raw encoded data for segments for which decoding failed. A statistical model for the requested segment is updated using the combined result. The requested segment is decoded using the updated statistical model.

A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.

A quantum computing system includes a decoding unit that implements a low-cost “isolated fault decoder” in-line with a more sophisticated decoder in order to significantly reduce bandwidth consumption and a requisite amount of decoding hardware to perform error correction that achieves a target error correction rate. The isolated fault decoder receives a syndrome from a measurement circuit of the quantum computing system and implements logic to attempt to identify a set of faults that explain the syndrome and that also satisfy a fault isolation threshold restricting a proximity between each pair of faults in the set.

Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

This application discloses a neural network-based QEC decoding method. The method includes: obtaining error syndrome information of a quantum circuit; performing block feature extraction on the error syndrome information by using a neural network decoder, to obtain feature information; and performing fusion decoding processing on the feature information by using the neural network decoder, to obtain error result information, the error result information being used for determining a data qubit in which an error occurs in the quantum circuit and a corresponding error type. In this application, a block feature extraction manner is used, a quantity of channels of feature information obtained by each feature extraction is reduced, and inputted data of next feature extraction is reduced, which reduces a quantity of feature extraction layers in a neural network decoder. Therefore, a decoding time used by the neural network decoder is reduced, thereby achieving real-time error correction.