A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.

An inter-hamming difference analyzer for a memory array having a plurality of sections is provided. The inter-hamming difference analyzer includes a controller, a storage device and a comparator. The controller is configured to obtain contents of the plurality of sections operating in a first operating condition and a second operating condition. The storage device is configured to store the contents of the plurality of sections corresponding to the first operating condition. The comparator is configured to obtain a plurality of inter-hamming differences of the plurality of sections according to the number of unlike bits between the content of a first section of the plurality of sections corresponding to the second operating condition and the contents of a plurality of sections other than the first section stored in the storage device.

This disclosure discloses a fault tolerant and error correction decoding method and apparatus for a quantum circuit, and a chip. This disclosure relates to the field of artificial intelligence (AI) and quantum technologies. The method includes: obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit by using a quantum error correction (QEC) code; decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information that correspond to the actual error syndrome information; and determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

In some implementations, a memory device may encode a codeword that encodes multiple data bits, multiple parity bits, and at least one metadata bit. The memory device may perform a first decoding procedure using the codeword to determine a first decoded set of bits by using a first hypothesized value of the at least one metadata bit. The memory device may perform a second decoding procedure to determine a second decoded set of bits by using a second hypothesized value of the at least one metadata bit. The memory device may determine, using the first decoded set of bits and the second decoded set of bits, whether the first hypothesized value of the at least one metadata bit or the second hypothesized value of the at least one metadata bit is a value of the at least one metadata bit.

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

An operating method of a memory controller is provided. The operating method includes receiving a first read data and a second conversion information, the second conversion information including data obtained by converting a second read data based on a linear operation, and the first read data and the second read data including data read from same memory cells; converting the first read data based on the linear operation to generate a first conversion information; performing a logical operation on the first conversion information and the second conversion information to generate an operation information; performing an inverse operation of the linear operation on the operation information to generate a reliability information; and correcting an error of the first read data based on the first read data and the reliability information.

This application discloses a neural network-based QEC decoding method. The method includes: obtaining error syndrome information of a quantum circuit; performing block feature extraction on the error syndrome information by using a neural network decoder, to obtain feature information; and performing fusion decoding processing on the feature information by using the neural network decoder, to obtain error result information, the error result information being used for determining a data qubit in which an error occurs in the quantum circuit and a corresponding error type. In this application, a block feature extraction manner is used, a quantity of channels of feature information obtained by each feature extraction is reduced, and inputted data of next feature extraction is reduced, which reduces a quantity of feature extraction layers in a neural network decoder. Therefore, a decoding time used by the neural network decoder is reduced, thereby achieving real-time error correction.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

Methods and devices are disclosed for encoding source words and decoding codewords with LDPC matrices, comprising: receiving a 1×K source word row vector ū; and generating a 1×N codeword vector c=ū.Math.G, wherein G is a K×N generator matrix derived from a parity check matrix H.sub.l; and wherein H.sub.l is derived from a base parity check matrix H by summing different rows in the base parity check matrix H to obtain an intermediate parity check matrix, and applying a lifting matrix to the intermediate base parity check matrix to obtain H.sub.l.