Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.

A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2.sup.m) is represented by ; a lookup table f(.sup.j) for different power exponents of is established, where the value of j is selected from all the integers ranging from 0 to 2m1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(.sup.j).

A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a sequence of information symbols, generating a plurality of cyclic codewords each corresponding to a portion of the sequence of information symbols, jointly encoding the plurality of cyclic codewords to generate at least one combined codeword, and providing the combined codeword to a device. The at least one combined codeword may be generated through Galois Fourier Transform (GFT). In one embodiment, a method for joint decoding includes, in part, obtaining a sequence of encoded symbols, wherein the sequence of encoded symbols is generated through GFT, jointly decoding the sequence of encoded symbols using an iterative soft decision decoding algorithm to generate a decoded sequence, transforming the decoded sequence to generate a plurality of cyclic codewords, and decoding the plurality of cyclic codewords to generate a plurality of decoded information symbols.

A method for detecting errors is performed on a data string which includes an information portion and a redundancy portion. The information portion includes two or more sub-strings. The method includes generating respective redundancy words for each sub-string by encoding each sub-string with a separable robust code. A composite redundancy word is generated from respective redundancy words. An error is flagged when the redundancy portion of said data string differs from the composite redundancy word.

Examples disclosed herein relate to very large-scale integration (VLSI) circuit implementations of list decode circuits. In accordance with some examples disclosed herein, a device may include a first and second polynomial evaluation circuit, a field division circuit, a discrepancy filter, and an enhanced error locator polynomial (ELP) circuit. The first and second polynomial evaluation circuits may respectively evaluate a first and second polynomial output from a Berlekamp-Massey algorithm over a plurality of values in a finite field. The field division circuit may divide the outputs from the evaluations to generate a plurality of speculative discrepancy values for an additional iteration of the Berlekamp-Massey algorithm. The discrepancy filter circuit may filter the speculative discrepancy values down to a list of potentially valid discrepancy values that may be used by the enhanced ELP circuit to generate an enhanced ELP.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

For example, the present techniques may provide an energy-efficient multipurpose encryption engine capable of processing both AES and CRC algorithms using a shared Galois Field Computation Unit (GFCU). In an embodiment, an apparatus may comprise computation circuitry adapted to perform Galois Field computations and control circuitry adapted to control the computation circuitry so as to selectively compute either an Advanced Encryption Standard cipher or a Cyclic Redundancy Check.

Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF.sup.10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).