An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.

A method for repairing a single erasure in a Reed Solomon code in a system of a plurality of n storage nodes and a controller, wherein a content of each storage node is a codeword and each node stores a vector v. The method includes identifying a failed storage node; transmitting an index of the failed storage node to each surviving storage node; multiplying the content of each node i by a j-th component of a vector that is a permutation of elements of vector v that correspond to the surviving storage nodes; determining a trace map of the result and converting the result from an mr bit representation into a reduced representation of r bits; reconstructing the content of the failed storage node from the reduced representation of each surviving node's content; and outputting the reconstructed content of the failed storage node.

A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Disclosed apparatus and method improve the computational efficiency of encoding and decoding data having erasures according to a maximum distance separable (MDS) code based on a Reed-Solomon code. Thus, n encoded fragments are formed by multiplying k data fragments by an nk generator matrix for the MDS code. The code is formed by reducing, in the generator matrix to the extent possible, the size of the finite field to which entries belongin some cases to the base field having only two elements. In this way, unlike codes known in the art, the generator matrix has more than one column whose entries each take values in the finite field having two elements. In some cases, the generator matrix has a column whose entries each take values in one or more intermediate fields between the finite field having two elements and the encoding field.

An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.

Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF.sup.10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.

An encoding method, an encoder, and a decoder for dynamic power consumption control are provided. The encoder includes a control unit, an initial encoding unit, and L incremental encoding units. The control unit is configured to enable only the initial encoding unit in an RS (N.sub.0, K) operating mode to perform encoding or enable only the initial encoding unit and first j incremental encoding units in the L incremental encoding units in an RS (N.sub.j, K) operating mode to perform encoding. The initial encoding unit is configured to perform RS FEC encoding on m(x) to obtain a quotient D.sub.0(x) and a remainder R.sub.0(x) of x.sup.N.sub.0.sup.Km(x) relative to g.sub.0(x). An (h+1).sup.th incremental encoding unit is configured to obtain, according to a quotient D.sub.h(x) and a remainder R.sub.h(x), a quotient D.sub.h+1(x) and a remainder R.sub.h+1(x) of x.sup.N.sub.h+1.sup.Km(x) relative to g.sub.h+1(x).

Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.

A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.