Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF.sup.10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

Techniques for decoding potentially corrupted Reed-Solomon encoded messages are provided. To decode a message, an incoming message is classified into a group based on which symbols of the message have survived (a survival pattern). The same inversion matrix may be used for each survival pattern associated with a single group. This reduces the amount of work required and data that is to be stored in order to perform the matrix multiplication that decodes the message.

A decoding method includes that when encoding at a sending terminal, for a m-order primitive polynomial P(x), a primitive field element in galois field GF(2.sup.m) is represented by ?; a lookup table f(?.sup.j) for different power exponents of ? is established, where the value of j is selected from all the integers ranging from 0 to 2m?1, with a total number of 2m; a generator polynomial G(x) is expanded to obtain a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ?; a remainder polynomial R(x), obtained by dividing code word polynomial Q(x) by the generator polynomial G(x), is a polynomial with respect to x, with coefficients being an addition or subtraction of the power exponents of ?; and the coefficients of the generator polynomial G(x) and the remainder polynomial R(x) are both calculated using data found in the lookup table f(?.sup.j).

To reduce the processing amount of a field multiplication. a denotes a k-th order vector whose elements are a.sub.0, . . . , a.sub.k1 (a.sub.0, . . . , a.sub.k1GF(x.sup.q)). A denotes an n-by-k matrix formed by vertically connecting a identity matrix and a Vandermonde matrix. b denotes an n-th order vector obtained by multiplying the vector a and the matrix A whose elements are b.sub.0, . . . , b.sub.n1 (b.sub.0, . . . , b.sub.n1GF(x.sup.q)). A vector conversion part 11 generates a -th order vector b using elements b.sub.p0, . . . , b.sub.p1 of the vector b. An inverse matrix generation part 12 generates a -by- inverse matrix A.sup.1. A plaintext computation part 13 computes elements a.sub.e0, . . . , a.sub.e1 of the vector a by multiplying the vector b and the inverse matrix A.sup.1.

Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF.sup.10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

To reduce the processing amount of a field multiplication. A matrix application apparatus computes a vector b by multiplying a vector a and a matrix A, provided that a denotes a k-th order vector having elements a.sub.0, . . . , a.sub.k-1 (a.sub.0, . . . , a.sub.k-1GF(x.sup.q)), b denotes an m-th order vector having elements b.sub.0, . . . , b.sub.m-1 (b.sub.0, . . . , b.sub.m-1GF(x.sup.q)), and A denotes a m-by-k Vandennonde matrix. A polynomial multiplication part computes a value b.sub.i. An order reduction part designates g.sub.ih.sub.if as the value b.sub.i by using a polynomial h.sub.i obtained by dividing a part of the value b.sub.i having an order equal to or higher than q by X.sup.q and a polynomial g.sub.i formed by a part of the value b.sub.i having an order lower than q.

Operational n-state digital circuits and n-state switching operations with n and integer greater than 2 execute Finite Lab-transformed (FLT) n-state switching functions to process n-state signals provided on at least 2 inputs to generate an n-state signal on an output. The FLT is an enhancement of a computer architecture. Cryptographic apparatus and methods apply circuits that are characterized by FLT-ed addition and/or multiplication over finite field GF(n) or by addition and/or multiplication modulo-n that are modified in accordance with reversible n-state inverters, and are no longer known operations. Cryptographic methods processed on FLT modified machine instructions include encryption/decryption, public key generation, and digital signature methods including Post-Quantum methods. They include modification of isogeny based, NTRU based and McEliece based cryptographic machines.

A method (400) of generating a cryptographic checksum for a message M(x) is provided. The method is performed by a communication device, such as a sender or a receiver, and comprises calculating (405) the cryptographic checksum as a first function g of a division of a second function of M(x), f(M(x)), modulo a generator polynomial p(x) of degree n, g(f(M(x)) mod p(x)). The generator polynomial is calculated (403) as p(x)=(1x).Math.P.sub.1(x), and P/(x) is a primitive polynomial of degree n1. The primitive polynomial is selected (402), based on a first cryptographic key, from the set of primitive polynomials of degree n1 over a Galois Field. By replacing a standard checksum with a cryptographic checksum, an efficient message authentication is provided. The proposed cryptographic checksum may be used for providing integrity assurance on the message, i.e., for detecting random and intentional message changes, with a known level of security. The proposed checksum is capable of detecting double-bit errors which may be introduced by a Turbo code decoder.

A system and method for performing erasure code data protection and recovery computations using simple arithmetic and data manipulation functions. Other embodiments set forth techniques for using the computation functions with a multiplicity of compact one-dimension table lookup operations. A set of assigned multi-threaded processor threads perform computations on data values in parallel to generate erasure code data protection information and to perform data recovery operations using available data and the data protection information. During normal operations, in one embodiment, threads may perform parallel computations using a small set of simple arithmetic operations and data manipulation functions. In other embodiments, the threads may also use a multiplicity of compact one-dimension lookup tables stored within the multi-threaded processor or otherwise accessible by the multi-threaded processor to perform the computations.

An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute parity check symbols by multiplying the partial syndromes by predetermined Lagrangian polynomial coefficients. The parity check symbol generation step may be performed in one clock cycle or multiple clock cycles.