In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may determine indices associated with m consecutive elements. In an aspect, each of the m consecutive elements may be associated with a different index. In addition, the apparatus may bit reverse a binary sequence associated with each of the m consecutive elements. In an aspect, each of the m consecutive elements may include a different binary sequence. Further, the apparatus may determine a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m elements. In addition, the apparatus may write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices.

An error correction circuit includes a syndrome calculator suitable for generating syndromes from an n-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.

A memory controller is a memory controller including an encoder that product-codes, with a linear code, data to be recorded in a memory section and a decoder that decodes product-coded data read out from the memory section. The encoder and the decoder share a parity generation circuit including a plurality of remainder calculating and retaining sections, each including a remainder calculation circuit by a generator polynomial and a retaining circuit that retains an output of the remainder calculation circuit.

Syndrome calculation circuitry for a decoder of codewords having a first number of symbols, where the decoder receives a second number of parallel symbols, and where the first number is not evenly divisible by the second number, includes multipliers equal in number to the second number. Each multiplier multiplies a symbol by a coefficient based on a root of a field of the decoder. The multipliers are divided into a number of groups determined as a function of a modulus of the first number and the second number. Adders equal in number to the groups add outputs of multipliers in respective ones of the groups. Accumulation circuitry accumulates outputs of the adders. Output circuitry adds outputs of the adders to an output of the accumulation circuitry to provide a syndrome. Selection circuitry directs outputs of the adders to the accumulation circuitry or the output circuity, and resets the accumulation circuitry.

A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

A system for hardware error-correcting code (ECC) detection or correction of a received codeword from an original codeword includes an error-detecting circuit configured to process a selection of symbols of the received codeword using a set of factors, the original codeword being recomputable from a corresponding said selection of symbols of the original codeword using the set of factors. The error-detecting circuit includes a hardware multiplier and accumulator configured to use the set of factors and the selection of symbols of the received codeword to recompute remaining symbols of the original codeword, and a hardware comparator configured to compare the recomputed remaining symbols of the original codeword with corresponding said remaining symbols of the received codeword and to output first results of this comparison.

The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p1), m(p2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output.

A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.