H04B1/71055

Symbol detection in shared wireless channel

A communication system includes a receiver to receive a signal with symbols encoded with a spreading code selected from a set of spreading codes, a filter to produce a filtered signal using a number of correlators less than a number of the spreading codes in the set of spreading codes, and a detector to detect the symbols transmitted by the transmitters from the filtered signal using sparse recovery with the dictionary matrix. The communication system also includes a processor to determine a minimum mean squared error (MMSE) matrix based on the set of spreading codes and a variance of noise in the channels, project the MMSE matrix to a low-dimensional space to produce a low-dimensional MMSE matrix, update the set of coefficients of set of correlators with the elements of the low-dimensional MMSE matrix, and update elements of a dictionary matrix based on the elements of the low-dimensional MMSE matrix.

Symbol Detection in Shared Wireless Channel
20190349222 · 2019-11-14 ·

A communication system includes a receiver to receive a signal with symbols encoded with a spreading code selected from a set of spreading codes, a filter to produce a filtered signal using a number of correlators less than a number of the spreading codes in the set of spreading codes, and a detector to detect the symbols transmitted by the transmitters from the filtered signal using sparse recovery with the dictionary matrix. The communication system also includes a processor to determine a minimum mean squared error (MMSE) matrix based on the set of spreading codes and a variance of noise in the channels, project the MMSE matrix to a low-dimensional space to produce a low-dimensional MMSE matrix, update the set of coefficients of set of correlators with the elements of the low-dimensional MMSE matrix, and update elements of a dictionary matrix based on the elements of the low-dimensional MMSE matrix

Regularized parameter adaptation
10469290 · 2019-11-05 · ·

An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

METHOD FOR MITIGATING INTERFERENCE AND INTERFERENCE MITIGATING RECEIVER

A method (200) for mitigating interference includes: receiving (201) a first signal (y.sub.1) comprising a first plurality of multipath transmissions from at least one radio cell at a first antenna port (A) and a second signal (y.sub.2) comprising a second plurality of multipath transmissions from the at least one radio cell at a second antenna port (B); generating (202) a first spatial component (h.sub.1A) of a first channel coefficient (h.sub.1) based on the first signal (y.sub.1) and a second spatial component (h.sub.1B) of the first channel coefficient (h.sub.1) based on the second signal (y.sub.2); generating (203) a covariance measure (R.sub.y) based on the first signal (y.sub.1) and the second signal (y.sub.2); and generating (204) a first spatial component (w.sub.1A) of a first weight (w.sub.1) for interference mitigation based on the covariance measure (R.sub.y), the first and second spatial components (h.sub.1A, h.sub.1B) of the first channel coefficient (h.sub.1) and a scalar correction value (C).

Multi-stage MISO circuit for fast adaptation

Systems and methods are disclosed for applying multi-stage multiple input single output (MISO) circuits for fast adaptation. An apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, a MISO circuit. The MISO circuit may include a first stage filter having a first number of taps and configured to filter signal samples received from the first reader and the second reader and produce first filtered samples. The MISO circuit may also include a second stage filter having a second number of taps greater than the first number, and be configured to receive the first filtered samples corresponding to the first reader and the second reader from the first filter stage, filter the first filtered samples to produce second filtered samples, and combine the second filtered samples to produce a combined sample output.

Methods and systems for performing radio-frequency signal noise reduction in the absence of noise models

Time-varying input signals are denoised by a neural network. The neural network learns features associated with noise added to reference signals. The neural network recognizes features of noisy time-varying input signals mixed with the noise that at least partially match at least some of the features associated with the noise. The neural network predicts denoised time-varying output signals that correspond to the time-varying input signals based on the recognized features of the noisy time-varying input signals that at least partially match at least some of the features associated with the noise.

Parallelized writing of servo RRO/ZAP fields
10276197 · 2019-04-30 · ·

An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.

Multi-signal realignment for changing sampling clock

An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.

PARALLELIZED WRITING OF SERVO RRO/ZAP FIELDS
20180366149 · 2018-12-20 · ·

An apparatus may include a first and second servo channels configured to output first and second position information to first and second writers, respectively, via a shared write path such that the first and second writers write first and second position information to first and second magnetic recording medium surfaces, respectively. In addition, the apparatus may include a controller configured to control the shared write path such that write access is changed between the first servo channel and second servo channel a plurality of times during a revolution of the first magnetic recording medium surface and second magnetic recording medium surface.

HYBRID TIMING RECOVERY
20180366155 · 2018-12-20 · ·

An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.