One example discloses s passive equalizer circuit, including: an input configured to receive an input signal having an input frequency band; a transfer function circuit configured to transform the input frequency band into an output frequency band; and an output configured to be coupled to an active equalizer circuit and carry an output signal having the output frequency band; wherein the transfer function circuit includes a variable impedance configured to adjust a mid-band frequency gain of the output signal.

A calibration circuit includes a replica summing circuit, a replica sampling circuit and a control circuit. The replica summing circuit is a replica of a sampling circuit in a serializer/deserializer (SerDes) interface and is configured to provide a summer output signal that is representative of a common mode voltage at an input of the SerDes interface. The replica sampling circuit is a replica of a sampling circuit in the SerDes interface. The replica sampling circuit includes a first input transistor having a gate coupled to the summer output signal and a second input transistor configured to provide an internal reference voltage at its drain. The drain of the second input transistor is coupled to a gate of the second input transistor. The control circuit is configured to control current flow in the replica summing circuit in response to a calibration signal output by the replica sampling circuit.