Provided is a digital equalizer which outputs a decision value corresponding to reception data transmitted from a data transmitter and is located in a data receiver. The digital equalizer includes at least one flip-flop which stores an adjacent bit sequence which is previous computing information; and a computing device which receives an output value of an analog to digital converter as a first input value, receives the adjacent bit sequence as a second input value, and outputs the decision value which is a binary value of the first input value by referring to a lookup table with respect to the first input value and the second input value.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

A receiver includes a decision feed forward equalization (DFFE) system that generates, based on a digital signal that includes at least one intersymbol interference (ISI) value introduced by a communication channel, a detected signal including a set of detected symbol values. The DFFE system cancels the at least one ISI value from the detected signal using the set of estimated transmitted symbols and a set of tap coefficients to obtain a compensated signal and a set of compensated symbol values.

A decision feedback equalizer includes a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.

A receiver unit comprising a signal input configured to receive a receive signal including a plurality of data symbols, a symbol detection circuit configured to detect a subset of data symbols, a reliability measuring circuit configured to determine a reliability value for the data symbols, a feedback loop configured to detect the subset of data symbols and the reliability value iteratively, and a signal output circuitry configured to determine output values of the subset of data symbols on the basis of the detected subset of data symbols and the determined reliability value.

A slicer circuit for use in a N-tap, S-bit symbol look-ahead decision feedback equalizer (DFE) wherein the slicer comprises overflow adders and sign adders, the slicer circuit including a first processing path for generating, based on a signal sample y(n), a most significant bit (MSB) for each of 2.sup.S*N possible output symbols of the DFE, the first processing path including (2.sup.S*N)/2 overflow adder circuits, and a second processing path for generating, based on the signal sample y(n), a least significant bit (LSB) for each of the 2.sup.S*N possible output symbols, the second processing path including 2.sup.S*N sign adder circuits.

A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

An integrated circuit may include a receiver configured to receive a first data signal based on an m.sup.th (where m is an integer of 1 or more) transmitter preset setting among a plurality of transmitter preset settings through an external link, and equalize and sample the first data signal; a receiver setting table including a plurality of combinations including values of a plurality of parameters related to the receiver; and a receiver control circuit configured to sequentially select the plurality of combinations with reference to the receiver setting table and set the plurality of parameters with the selected combinations.