Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

An equalizer includes: a channel estimator configured to generate a set of time-domain channel coefficients based on a receive signal; a frequency-domain transformer configured to generate a set of frequency-domain channel coefficients based on a frequency transform of the set of time-domain channel coefficients; an equalizer coefficient generator configured to generate a set of frequency-domain equalizer coefficients based on the set of frequency-domain channel coefficients; a time-domain transformer configured to generate a set of time-domain equalizer coefficients based on a time transform of the set of frequency-domain equalizer coefficients; and a filter configured to filter the receive signal based on a filter function that is based on the set of time-domain equalizer coefficients.

Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

The equalizer has a first differential pair having a first transistor and a second transistor and a second differential pair having a third transistor and a fourth transistor. A first terminal of the first transistor and a first terminal of the third transistor are connected to each other, and a first terminal of the second transistor and a first terminal of the fourth transistor are connected to each other, so that the first differential pair and the second differential pair have common input terminals. Also, resistors are respectively connected to second terminals of the first, second, third, and fourth transistors, a first zero point generation circuit is connected between the second terminal of the first transistor and the second terminal of the second transistor, and a second zero point generation circuit is connected between the second terminal of the third transistor and the second terminal of the fourth transistor.

Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.

A reception circuit includes a receiver, a noise boosting circuit and a buffer. The receiver generates a positive amplification signal and a negative amplification signal by amplifying a first input signal and a second input signal. The noise boosting circuit adjusts voltage levels of the positive amplification signal and the negative amplification signal based on the first input signal and the second input signal. The buffer generates an output signal by amplifying the positive amplification signal and the negative amplification signal.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

A reception circuit includes a receiver, a noise boosting circuit and a buffer. The receiver generates a positive amplification signal and a negative amplification signal by amplifying a first input signal and a second input signal. The noise boosting circuit adjusts voltage levels of the positive amplification signal and the negative amplification signal based on the first input signal and the second input signal. The buffer generates an output signal by amplifying the positive amplification signal and the negative amplification signal.

Methods, systems, and apparatus for EM communications. One of the apparatus includes a plurality of receive samplers arranged in parallel and configured to receive an amplitude modulated input signal, each sampler being clocked at a same rate but not a same phase, the rate being in relation with the input signal; a plurality of envelope extractors, wherein each envelop extractor is communicatively coupled to a respective output of one of the plurality of receive samplers, and wherein each envelope extractor is configured to extract the envelope of the input signal after sampling; and a combiner communicatively coupled to the envelope extractors to combine the signal envelopes sampled at their respective phases, creating a combined output that provides an approximate copy of the input signal envelope, providing an output signal for performing symbol synchronization.

The telemetry system used in the measurement while drilling (MWD) or logging while drilling (LWD) is essentially a digital communication system. The fact of the special and hostile drilling environment limits the use of many advanced techniques and equipment, and thus results in a low data transmission rate. While increasing the data rate for the MWD/LWD telemetry system becomes a primary focus, maintaining the system reliability and the decoding quality at a high data rate is equally challenging. This invention presents digital signal processing solutions to a high performance telemetry system with the high data rate, high system reliability, and high decoding quality.