Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Transmitting device for a wireless communication system and method therein for transmitting data. The transmitting device comprises a processor, configured to: obtain a channel response (h); determine pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2) of a pre-processor structure, based on the obtained channel response (h); and pre-process the data, based on the pre-processor structure and the determined pre-processing coefficients (g.sub.0, g.sub.1, g.sub.2). The transmitting device comprises a transmitter, configured to transmit the pre-processed data.

A method of determining filter coefficients of an equalizer circuit for equalizing a non-linear electronic system is described. The equalizer circuit includes a Volterra filter circuit. Further, an equalizer circuit for equalizing a non-linear electronic system and an electronic device are described.

An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

Systems, methods, and instrumentalities are disclosed for separating a channel and data without the use of reference signals. For example, a wireless transmit/receive unit (WTRU) may determine a first orthogonal frequency-division multiplexing (OFDM) symbol based on a data vector. The WTRU may determine a second OFDM symbol by applying a circular time-inverse operation and a conjugate operation to the first OFDM symbol. The WTRU may send the first OFDM symbol and the second OFDM symbol. The first and the second OFDM symbols may be sent to consecutively. Discrete Fourier Transform (DFT)-spread and nonlinear preprocessing (exponential transformation at the transmitter) may be used and/or peak-to-average power ratio (PAPR) may be reduced via randomizer block at the receiver.

The presently-disclosed solution enables continuous time linear equalizer (CTLE) tuning without needing to perform bit error rate (BER) measurements. Because time consuming BER measurements are avoided, the CTLE tuning may be performed more rapidly as to reduce substantially the time required for link training. Furthermore, this solution re-uses decision feedback equalizer (DFE) adaptation circuitry so as to be highly efficient in its implementation. One embodiment relates to a method that tunes the CTLE based on results from the adaptation of the tap values of the DFE. Another embodiment relates to an apparatus that includes an interface for a control module to control a setting of a CTLE and an adaptation engine for a DFE. The value for the setting of the CTLE is selected using the adapted tap 1 value of the DFE as a figure of merit. Other embodiments and features are also disclosed.