A receiver in the present disclosure includes: a first input end, N first output ends, N baseband signal recovery modules, and a multiple-input multiple-output equalization module. Each baseband signal recovery module includes two second output ends; one second output end of each baseband signal recovery module is configured to output a baseband signal; and the other second output end is configured to output data enabling control information. The multiple-input multiple-output equalization module is configured to: control, based on N pieces of data enabling control information, a time sequence of N baseband signals entering the multiple-input multiple-output equalization module for equalization filtering processing, and perform equalization filtering processing on the N baseband signals by using N transmitters as references to obtain recovered data of the N transmitters. According to the embodiments of the present disclosure, asynchronous multi-transmitter data is received.

In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

A signal processing system and method, and an apparatus are provided. A phase recovery apparatus may be used to: receive a feedback signal fed back by an information iteration apparatus, perform, based on the feedback signal, phase recovery on a signal output by an equalizer, and output a phase-recovered signal to a post filtering apparatus, so that the post filtering apparatus performs noise filtering on the phase-recovered signal, and outputs a noise-filtered signal to the information iteration apparatus. To be specific, the phase recovery may be performed, based on the signal fed back by the information iteration apparatus, on the signal output by the equalizer. Because output of the information iteration apparatus is more accurate in determining the signal, precision of the phase recovery can be improved, cycle skipping is reduced, and input signal quality of the post filtering apparatus is improved.

A digital television (DTV) transmitting system is provided that includes an encoder, a group formatter, a packet formatter and a transmission unit. The group formatter forms data groups where the plurality of second known data sequences are spaced 16 segments apart within at least one of the data groups that includes a transmission parameter inserted between the first known data sequence and the plurality of second known data sequences and the first known data sequence has a first M-symbol sequence and a second M-symbol sequence, the first M-symbol sequence and the second M-symbol sequence have a first pattern, each of the plurality of second known data sequences has a second pattern other than the first pattern, and the second pattern is positioned from a last symbol to a previous N symbol in each of the plurality of second known data sequences.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

An apparatus in a signal receiver, such as an optical signal receiver, is provided. An adaptive equalizer provides an equalized output indicative of a received signal. A feedback component receives the equalized output and provides feedback to the adaptive equalizer. A carrier recovery component receives the equalized output from the adaptive equalizer provides estimates of symbols. The carrier recovery component is partially or fully disjoint from the feedback component, thus removing the carrier recovery component from equalizer the feedback loop. The feedback component can include an initial carrier recovery component and a phase rotation and detection component. The initial carrier recovery component generates a carrier recovery output based on the equalized output. The phase rotation and detection component performs a phase rotation based on the carrier recovery output.