An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A receiver in the present disclosure includes: a first input end, N first output ends, N baseband signal recovery modules, and a multiple-input multiple-output equalization module. Each baseband signal recovery module includes two second output ends; one second output end of each baseband signal recovery module is configured to output a baseband signal; and the other second output end is configured to output data enabling control information. The multiple-input multiple-output equalization module is configured to: control, based on N pieces of data enabling control information, a time sequence of N baseband signals entering the multiple-input multiple-output equalization module for equalization filtering processing, and perform equalization filtering processing on the N baseband signals by using N transmitters as references to obtain recovered data of the N transmitters. According to the embodiments of the present disclosure, asynchronous multi-transmitter data is received.

An apparatus in a signal receiver, such as an optical signal receiver, is provided. An adaptive equalizer provides an equalized output indicative of a received signal. A feedback component receives the equalized output and provides feedback to the adaptive equalizer. A carrier recovery component receives the equalized output from the adaptive equalizer provides estimates of symbols. The carrier recovery component is partially or fully disjoint from the feedback component, thus removing the carrier recovery component from equalizer the feedback loop. The feedback component can include an initial carrier recovery component and a phase rotation and detection component. The initial carrier recovery component generates a carrier recovery output based on the equalized output. The phase rotation and detection component performs a phase rotation based on the carrier recovery output.

A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients

Aspects of the disclosure relate to inter-link interference cancellation for reducing or mitigating interference from signals in different directions (e.g., uplink and downlink directions). A wireless communication device (i.e., a victim device subject to inter-link interference) may determine a time offset or lead time of an interfering signal from an offending device. Based on the determined time offset, the victim device may perform interference cancellation or suppression to reduce or mitigate the interference of the interfering signal. Other aspects, embodiments, and features are also claimed and described.

A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.

Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

An electronic device includes a clock recovery circuit, a converter circuit, and a decoder circuit. The clock recovery circuit generates a reference clock. The converter circuit generates a conversion value that corresponds to a difference between a phase of reception data and a phase of the reference clock. The decoder circuit analyzes a reception characteristic of an antenna based on conversion values that corresponds to a start-of-frame (SOF) marker. The decoder circuit decodes a conversion value that corresponds to encoded data following the SOF marker in the reception data, with reference to the analyzed reception characteristic, into a digital value.