A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data.

Methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. In particular, a preamble for transmission in a sequence of symbols over a multi-wire communications interface, such as a MIPI C-PHY interface, is constructed to include one or more symbols each having a single state transition symbols for signaling a particular calibration preamble from a transmitter to a receiver over the multi-wire communications interface. The preamble, having only single state transition symbols, improves reliability of decoding the symbols at a receiver, including reception and decoding without the use of a calibration clock.

Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

An integrated circuit for supporting a high-speed communications link. The integrated circuit may include equalization and hybrid phase detection circuitry configured to perform clock data recovery (CDR) for high-order pulse amplitude modulated (PAM) signals. The phase detector circuit includes partial oversampling sampling circuitry that generates edge samples an incoming PAM signal and Baud rate sampling circuitry that generates error and data samples on the PAM signals. Edge, data, and error samples may be passed to error minimization circuitry within an adaptation circuit that may dynamically compute contributions to a weighted phase error by oversampling and Baud rate components. The adaptation circuit may use the weighted phase error to adjust the phase of a recovered clock signal used to recover data transmitted through the high speed communications link.

A signal processing system and method, and an apparatus are provided. A phase recovery apparatus may be used to: receive a feedback signal fed back by an information iteration apparatus, perform, based on the feedback signal, phase recovery on a signal output by an equalizer, and output a phase-recovered signal to a post filtering apparatus, so that the post filtering apparatus performs noise filtering on the phase-recovered signal, and outputs a noise-filtered signal to the information iteration apparatus. To be specific, the phase recovery may be performed, based on the signal fed back by the information iteration apparatus, on the signal output by the equalizer. Because output of the information iteration apparatus is more accurate in determining the signal, precision of the phase recovery can be improved, cycle skipping is reduced, and input signal quality of the post filtering apparatus is improved.

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Embodiments of the present disclosure relate to methods and device for receiving PAM data stream. In an embodiment, a method comprises receiving a signal stream modulated with pulse amplitude modulation (PAM) associated with a plurality of bit patterns; determining boundary voltages for the plurality of bit patterns; and calibrating, based on the boundary voltages, a threshold voltage for use in recognition of the plurality of bit patterns. In this way, bit patterns may be accurately recognized based on the calibrated threshold voltage.

Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

Various aspects described herein relate to techniques and modulation schemes used in near-field communications systems. A method for near-field communications is provided that may include receiving a signal including an unmodulated carrier frequency, locking onto the unmodulated carrier frequency, and recovering a data clock frequency from the unmodulated carrier frequency based on a relationship between the data clock frequency and the unmodulated carrier frequency.