An integrated circuit (IC) memory device includes receiver circuitry to receive write data from a memory controller. The receiver circuitry includes equalization circuitry having at least one tap to equalize the write data. The equalization circuitry includes a tap weight adapter circuit to adaptively generate a tap weight for the tap from an edge analysis of previously received write data.

This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A receiver device includes circuitry and memory. The circuitry converts an input signal into a data signal that includes data symbols transmitted in successive unit intervals (UIs), determines a first threshold associated with a first symbol type, adjusts a gain of the receiver device such that an average amplitude of data signal samples, when receiving data symbols having the first symbol type, corresponds to the first threshold, determines a second threshold that corresponds to an average amplitude of the data signal samples when data symbols of a current UI have the first symbol type and data symbols of a first UI, at a first determined time distance from the current UI, have a second symbol type, and computes, as a first cursor value associated with the first UI, a first difference between the first threshold and the second threshold, multiplied by a first constant.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.