A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A communication apparatus includes an input terminal, an output terminal, and an interference reduction circuit. The interference reduction circuit is coupled between the input terminal and the output terminal. The interference reduction circuit receives a time-varying data signal. The interference reduction circuit acquires first partial data from the data signal at a first time, and generates a first level-shifted result and a second level-shifted result according to the first partial data. The interference reduction circuit is further configured to acquire second partial data from the data signal at a second time. The interference reduction circuit selects one of the first level-shifted result and the second level-shifted result as a selected result according to the second partial data, and sends the selected result to the output terminal.

An apparatus comprises: a CDR sub-system comprising: an FFE; a decision component coupled to the FFE; a subtractor coupled to the FFE and the decision component; and a tap weight updater coupled to the subtractor and the FFE; and a PR-MLSE component coupled to the CDR sub-system. A method comprises: converting an optical signal with a first modulation format to an analog electrical signal; converting the analog electrical signal to a first digital signal; equalizing the first digital signal into a second digital signal with a second modulation format, wherein the second modulation format has more levels than the first modulation format; and performing CDR on the second digital signal.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.