An apparatus comprises: a CDR sub-system comprising: an FFE; a decision component coupled to the FFE; a subtractor coupled to the FFE and the decision component; and a tap weight updater coupled to the subtractor and the FFE; and a PR-MLSE component coupled to the CDR sub-system. A method comprises: converting an optical signal with a first modulation format to an analog electrical signal; converting the analog electrical signal to a first digital signal; equalizing the first digital signal into a second digital signal with a second modulation format, wherein the second modulation format has more levels than the first modulation format; and performing CDR on the second digital signal.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A modulator and demodulator pair may switch configurations without introducing errors as a result of the switch. Different configurations may, for example, correspond to different symbol rates and/or different amounts of controlled inter-symbol interference (ISI) introduced to the transmitted signal. For example, a first configuration may use be a near-zero ISI configuration (e.g., using Nyquist signaling) and a second configuration may introduce a significant (e.g., amount that would result in errors above a desired threshold if demodulation relied on symbol-by-symbol slicing) but controlled amount of ISI (e.g., using partial response or faster-than-Nyquist-rate signaling). Switching between modulator/demodulator configurations may be needed to maintain a stable link in the case of dynamic channels. At any given time, a modulator and demodulator pair may, for example, switch to a configuration that provides maximal throughput for the current channel conditions.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.