A high data rate, high sensitivity, low power optical link using low-bandwidth components and low-bandwidth E/O drivers and receivers and method of building same. The method is based on the idea of making the optical part of the link look like a bandwidth limited lossy electrical channel, so that the powerful equalization methods used in the wireline electrical links can be applied to recover the transmitted data in a situation with low bandwidth and/or high loss and strong inter-symbol interference. Linear and non-linear optical channel components, E/O drivers and receivers can benefit from the apparatus and the methods of the invention.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A transmitter may be operable to generate a sequence of symbols which may comprise information symbols and one or more pilot symbols. The transmitter may transmit the information symbols at a first power and transmit the one or more pilot symbols at a second power. In instances when a particular performance indicator is below a determined threshold, the first power may be set to a first value and the second power may be set to zero value. In instances when the particular performance indicator is above the determined threshold, the first power may be set to a second value and the second power may be set to a non-zero value. A value of the first power and a value of the second power may be based on an applicable average power limit determined by a communications standard with which the transmitter is to comply.

An integrated circuit (IC) chip includes transfer circuitry to transfer signals between the IC chip and a second IC chip. The transfer circuitry includes equalization circuitry having at least one tap to equalize the signals. The equalization circuitry includes a tap weight adapter circuit to generate a respective tap weight for each of the at least one tap based on edge information of previously transferred signals.

A test system implemented method of equalizing a digital signal under test (SUT) results in a waveform representation of the output of a Partial Response Maximum Likelihood Sequence Equalizer (PR-MLSE). The method includes applying the SUT, having greater than one symbol period of inter-symbol interference (ISI), to a feed forward equalizer to obtain a Partial Response equalized sequence r.sub.k having an ISI characterized as (1+D), wherein r.sub.k denotes the kth equalized sample of the waveform, sampled at the symbol rate, and is a programmable variable. The method further includes obtaining a known symbol sequence, m.sub.k, as a user input to the system, and determining y(capped).sub.k, the kth sample of the PR-MLSE equivalent waveform, in accordance with the following equation, ${\stackrel{}{y}}_k=\frac{r_k+r_{k+1}-\left(m_{k-1}+m_{k+1}\right)}{1+{}^2}.$