Disclosed is a frequency characteristic adjusting circuit disposed between an optical circuit element and a drive circuit driving the optical circuit element. The frequency characteristic adjusting circuit includes a capacitor, and two or more series circuits having a resistor and a switch, the two or more series circuits being connected in parallel with the capacitor, where resistance with respect to the switch that is turned on is changed according to an output voltage of the drive circuit by changing ON or OFF of the switch such that electric charge at a contact point between the optical circuit element and the capacitor is adjusted to be constant regardless of the output voltage of the drive circuit.

A method of designing a digital filter for example for use in an FBMC/OQAM telecommunications system, with a target overlapping factor and meeting a specified signal to interference ratio is described, whereby a candidate filter design defined by an impulse response, satisfying the Nyquist criterion and having an overlapping factor higher than the target is selected, and the time and frequency coefficients of its impulse response inverted to define a new filter design; and truncating the impulse response defining said new filter design to the minimum number of coefficients achieving said specified signal to interference ratio.

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

It is difficult to obtain a demodulated signal with high signal quality in a digital optical receiver because it is difficult to compensate for each of different types of waveform distortion by a high-performance equalization process; therefore, a digital signal processor according to an exemplary aspect of the present invention includes a fixed equalization means for performing a distortion compensation process based on a fixed equalization coefficient on an input digital signal; an adaptive equalization means for performing an adaptive distortion compensation process based on an adaptive equalization coefficient on an equalized digital signal output by the fixed equalization means; a low-speed signal generation means for generating a low-speed digital signal by intermittently extracting one of the input digital signal and the equalized digital signal; a low-speed equalization coefficient calculation means for calculating a low-speed equalization coefficient to be used for a distortion compensation process of the low-speed digital signal; and a fixed equalization coefficient calculation means for calculating the fixed equalization coefficient by using at least a predetermined coefficient out of the low-speed equalization coefficient and the predetermined coefficient.

Systems and methods for creating and using a first and second group of training sequences in a training-aided single-carrier frequency domain equalization system. The first group of training sequences are conventional training sequences and the second group of training sequences are 90-rotated versions of the first group of training sequences.

Systems and methods for creating and using a first and second group of training sequences in a training-aided single-carrier frequency domain equalization system. The first group of training sequences are conventional training sequences and the second group of training sequences are 90-rotated versions of the first group of training sequences.

An anti-aliasing channel estimation apparatus and method and a receiver where the anti-aliasing channel estimation method includes: performing clock recovery and data synchronization on a received multicarrier signal with channel aliasing, to obtain a synchronized time-domain signal and a sampling phase; calculating an estimation signal after passing through a channel and being aliased based on a training sequence and the sampling phase, and obtaining a channel response and an aliasing signal response of each subcarrier of the multicarrier signal based on the estimation signal and the frequency-domain signal. Therefore, channel estimation may be performed on the multicarrier signal with channel aliasing, influence of the channel aliasing on the bit error rate may be lowered, and transmission quality of the system may be improved.

An adaptive recursive filter is disclosed. The filter includes a filtering device to iteratively apply a recursive filter to signal frames corresponding to portions of a sampled broadband signal. Each iteration of the recursive filter may include generating an autocorrelation signal of an input signal frame, calculating a ratio of a magnitudes of a pair of successive points of the autocorrelation signal, comparing the ratio to a selected signal detection threshold such that a value of the ratio greater than a threshold indicates at least one signal of interest, calculating an energy-weighted average frequency of the input signal frame as a frequency of interest, comparing a spectral energy of the input signal frame at the frequency of interest to spectral energies of surrounding frequencies to identify a frequency of a narrowband interference signal, and filtering the input signal frame at the identified frequency to remove the identified narrowband interference signal.

Generating first and second discharge control signals in response to a clock signal and an input voltage signal, the first and second discharge control signals decreasing at different rates to a threshold level during a first time period, wherein a difference in rates is determined by the input voltage signal, generating a differential voltage on a pair of nodes during the first time period by selectively controlling a respective amount of discharge of an initial charge on each node of the pair of nodes by applying the first and second discharge control signals to respective transistors in a differential transistor pair connected to the pair of nodes, and maintaining the differential voltage on the pair of nodes during a subsequent time period, and generating an amplified differential voltage during at least a portion of the subsequent time period by amplifying the differential voltage.

Disclosed is a frequency characteristic adjusting circuit disposed between an optical circuit element and a drive circuit driving the optical circuit element. The frequency characteristic adjusting circuit includes a capacitor, and two or more series circuits having a resistor and a switch, the two or more series circuits being connected in parallel with the capacitor, where resistance with respect to the switch that is turned on is changed according to an output voltage of the drive circuit by changing ON or OFF of the switch such that electric charge at a contact point between the optical circuit element and the capacitor is adjusted to be constant regardless of the output voltage of the drive circuit.