A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.

A semiconductor device includes a nitride semiconductor layer, an insulating layer provided on a surface of the nitride semiconductor layer, and a metal electrode in contact with the surface through an opening penetrating the insulating layer. The insulating layer includes a first SiN film having a concentration of chlorine (Cl) of 1×10.sup.20 [atoms/cm.sup.3] or more and a thickness of 30 nm or less, and a second SiN film having a concentration of chlorine (Cl) of 1×10.sup.19 [atoms/cm.sup.3] or less.

A method for forming an oligomer-containing layer on a substrate and in a concave portion formed on the substrate by performing a cycle a predetermined number of times under a first temperature, the cycle including supplying a precursor gas to the substrate, and supplying first and second nitrogen- and hydrogen-containing gases to the substrate, so an oligomer including an element in at least one selected from the group of the precursor gas, and the first and second nitrogen-hydrogen-containing gasses, flowed in the concave portion, and (b) forming a film to fill the inside of the concave portion by post-treating the substrate, which has the oligomer-containing layer formed on the surface of the substrate and in the concave portion, under a second temperature not less than the first temperature, so that the oligomer-containing layer formed in the concave portion is modified to form the film.

A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

In general, according to one embodiment, there is provided a semiconductor device including a substrate, an insulating layer formed above the substrate, and a conductive layer provided in the insulating layer. The insulating layer includes at least one cellulose fiber.

An etching method includes: preparing a substrate including a first region containing silicon and nitrogen, and a second region containing silicon and oxygen; and etching the second region while firming a tungsten-containing protective layer on the first region, by exposing the first and second regions to plasma generated from a processing gas containing carbon, fluorine, and tungsten.

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

Method for producing coating composition applied to patterned resist film in lithography process for solvent development to reverse pattern. The method including: step obtaining hydrolysis condensation product by hydrolyzing and condensing hydrolyzable silane in non-alcoholic hydrophilic solvent; step of solvent replacement wherein non-alcoholic hydrophilic solvent replaced with hydrophobic solvent for hydrolysis condensation product. Method for producing semiconductor device, including: step of applying resist composition to substrate and forming resist film; step of exposing and developing formed resist film; step applying composition obtained by above production method to patterned resist film obtained during or after development in step, forming coating film between patterns; step of removing patterned resist film by etching and reversing patterns. Production method that exposure is performed using ArF laser (with wavelength of 193 nm) or EUV (with wavelength of 13.5 nm). Production method that development is negative development with organic solvent.

A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.