A topology-selective deposition method is disclosed. An exemplary method includes providing an inhibition agent comprising a first nitrogen-containing gas, providing a deposition promotion agent comprising a second nitrogen-containing gas to form an activated surface on one or more of a top surface, a bottom surface, and a sidewall surface relative to one or more of the other of the top surface, the bottom surface, and the sidewall surface, and providing a precursor to react with the activated surface to thereby selectively form material comprising a nitride on the activated surface.

Described herein are boron-containing precursor compounds, and compositions and methods comprising same, for forming boron-containing films. In one aspect, the film is deposited from at least one precursor having the following Formula I or II described herein. ##STR00001##

A process for manufacturing a silicon carbide device from a body of silicon carbide having a back surface, wherein a first layer of a first metal is formed on the back surface of the body; a second layer of a second metal, different from the first metal, is formed on the first layer to form a multilayer, the first or the second metal being nickel or a nickel alloy and forming a nickel-based layer, another of the first or the second metal being a metal X, capable to form stable compounds with carbon and forming an X-based layer; and the multilayer is annealed to form a mixed layer including nickel silicide and at least one of X carbide or a metal X-carbon ternary compound.

Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO.sub.2 and SiN can be selectively etched using a plasma formed in an Hz-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO.sub.2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO.sub.2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% Hz. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (Al.sub.xGa.sub.1-x).sub.yO.sub.z, wherein 0≤x≤1, 1≤y≤3, and 2≤z≤4, wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a Pna21 space group, and wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Embodiments of the present application relate to a method for manufacturing a semiconductor structure, includes: forming a contact metal layer on a silicon substrate; performing a plasma treatment process, and forming an oxygen isolation layer on a surface of the contact metal layer; and performing a silicidation reaction process, and converting the contact metal layer into a metal silicide layer.

According to the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

A method for manufacturing a semiconductor memory includes: providing a portion to be processed, and performing a preset process step on the portion to be processed at least after a minimum waiting time; before performing the preset process step, performing a thermal oxidation process on the portion to be processed; and before performing the preset process step, performing a cleaning process, the cleaning process being used to remove oxides from the surface of the portion to be processed, the oxides being wholly or partly generated by the thermal oxidation process.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.