A method for processing a substrate includes positioning a silicon substrate in a deposition chamber. One or more intermediate layers are deposited on a surface of the silicon. The one or more intermediate layers can include strontium, which combines with the silicon to form strontium silicide. Alternatively, the one or more intermediate layers comprise germanium. A layer of amorphous strontium titanate is deposited on the one or more intermediate layers in a transient environment in which oxygen pressure is reduced while temperature is increased. The substrate is then exposed to an oxidizing and annealing atmosphere that oxidizes the one or more intermediate layers and converts the layer of amorphous strontium titanate to crystalline strontium titanate.

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

The invention provides a process for forming crack-free dielectric films on a substrate. The process comprises the application of a dielectric precursor layer of a thickness from about 0.3 μm to about 1.0 μm to a substrate. The deposition is followed by low temperature heat pretreatment, prepyrolysis, pyrolysis and crystallization step for each layer. The deposition, heat pretreatment, prepyrolysis, pyrolysis and crystallization are repeated until the dielectric film forms an overall thickness of from about 1.5 μm to about 20.0 μm and providing a final crystallization treatment to form a thick dielectric film. The process provides a thick crack-free dielectric film on a substrate, the dielectric forming a dense thick crack-free dielectric having an overall dielectric thickness of from about 1.5 μm to about 20.0 μm.

The present invention relates to a method of manufacturing a ferrite rod. The method comprises etching cavities into two semiconductor substrates and depositing ferrite layers into the cavities. The semiconductor substrates are attached to each other such that the ferriote layers form a ferrite rod. The present invention employs conventional photolithography and bulk isotropic micromachining of semiconductor wafers to precisely and repeatably form a template or mold, into which magnetic material can be deposited to form a Faraday rotation or phase-shifting element.

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 10.sup.5 seconds and the data rewrite withstand property of not less than 10.sup.8 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts.

[Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca. Sr, Bi, Ta and oxygen atoms, the metal is Ir or Pt or an alloy of Ir and Pt, or Ru, and the annealing for ferroelectric crystallization is performed in a mixed gas having oxygen added to nitrogen or a mixed gas having oxygen added to argon.

The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.

A residual stress in a PZT type ferroelectric film 12 formed on a substrate body 11 by a sol-gel process is −14 MPa to −31 MPa, and the ferroelectric film 12 is crystal oriented in a (100) plane.

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

[Problem] To provide a gate insulating film forming composition comprising a polysiloxane, which forms a gate insulating film having excellent characteristics such as high dielectric constant and high mobility. [Means for Solution] The gate insulating film forming composition comprises (I) a polysiloxane, (II) barium titanate, and (III) a solvent, wherein the content of the barium titanate is 30 to 80 mass % based on the total mass of the polysiloxane and the barium titanate.