Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.

A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

A memory device includes a substrate, a buried word line, a connecting structure, an air gap, and a first dielectric layer. The buried word line is disposed in the substrate. The connecting structure is disposed on the buried word line. The air gap is disposed on the buried word line and is adjacent to the connecting structure. The first dielectric layer is disposed on the connecting structure and the air gap, wherein the buried word line, the connecting structure, and the first dielectric layer are disposed in the first direction, which is substantially perpendicular to the top surface of the substrate.

There is provided a technique that includes: forming a first film to have a first predetermined film thickness over a substrate by performing a first cycle a first predetermined number of times, the first cycle including non-simultaneously performing: (a1) forming an oxynitride film by supplying a first film-forming gas to the substrate; and (a2) changing the oxynitride film into a first oxide film by supplying a first oxidizing gas to the substrate to oxidize the oxynitride film.

A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Disclosed is a semiconductor device and a method of manufacturing the said semiconductor device. The semiconductor device comprises a plurality of layers. The method of fabricating the semiconductor device comprises obtaining a substrate layer, arranging a first corresponding crystalline terminating oxide layer on the substrate layer, arranging at least one semiconductor layer on the first crystalline terminating oxide layer, arranging a second corresponding crystalline terminating oxide layer on the at least one semiconductor layer, and arranging an electrical insulating layer on the second crystalline terminating oxide layer.

Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Disclosed is a semiconductor device and a method of manufacturing the said semiconductor device. The semiconductor device comprises a plurality of layers. The method of fabricating the semiconductor device comprises obtaining a substrate layer, arranging a first corresponding crystalline terminating oxide layer on the substrate layer, arranging at least one semiconductor layer on the first crystalline terminating oxide layer, arranging a second corresponding crystalline terminating oxide layer on the at least one semiconductor layer, and arranging an electrical insulating layer on the second crystalline terminating oxide layer.

The present disclosure provides a transistor, a transistor forming method thereof, and a semiconductor device. The transistor forming method comprises providing a substrate, the substrate comprising a first region for forming a source region and a second region for forming a drain region; forming a gate groove in the substrate to separate the first region and the second region, a part of the substrate along the bottom of the gate groove being used for constituting an embedded channel region of a transistor; forming a gate dielectric layer on the gate groove of the substrate to cover the embedded channel region and to extend to cover a side of the first region and a side of the second region in the gate groove; and forming a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove.