Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by an RF power operating at between about 50 W and 1,000 W, at a pulsing frequency below about 100,000 Hz, and at a duty cycle between about 5% and 95%. The methods may include forming a layer of material on the substrate. The layer of material may include a silicon-containing material.

A planarization system comprises a substrate chuck configured to hold a substrate, a superstrate chuck configured to hold a superstrate, a planarizing head configured to support the superstrate chuck, a positioning system configured to cause the superstrate to come into contact with formable material dispensed on the substrate to form a multilayer structure, the multilayer structure including the superstrate, a film of the formable material, and the substrate, and an annular light source disposed between an upper end of the planarizing head and the substrate chuck. The annular light source is configured to emit light onto an outer annular region of the multilayer structure without emitting the light onto an inner central region of the multilayer structure. The inner central region is located radially inward relative to the outer annular region.

A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

A method includes forming a multi-layer mask over a dielectric layer. Forming the multi-layer mask includes forming a bottom layer over the dielectric layer. A first middle layer is formed over the bottom layer. The first middle layer includes a first silicon-containing material. The first silicon-containing material has a first content of Si—CH.sub.3 bonds. A second middle layer is formed over the first middle layer. The second middle layer includes a second silicon-containing material. The second silicon-containing material has a second content of Si—CH.sub.3 bonds less than the first content of Si—CH.sub.3 bonds.

A substrate treatment method for treating a substrate, includes: applying a coating solution containing an organometallic complex, a solvent, and an additive to the substrate to form a solution film of the coating solution; heating the substrate on which the solution film of the coating solution has been formed, to form an organic constituent-containing metal oxide film being a metal oxide film containing an organic constituent contained in the additive; performing dry etching using the organic constituent-containing metal oxide film as a mask; removing the organic constituent in the organic constituent-containing metal oxide film after the dry etching; and removing, by wet etching, a film obtained by removing the organic constituent from the organic constituent-containing metal oxide film.

The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

A technique for obtaining good film quality in forming a silicon-oxide-containing insulating film as a coating film on a substrate. A coating liquid containing polysilazane is applied to a wafer, a solvent in the coating liquid is volatilized, and then the coating film is irradiated with ultraviolet rays under a nitrogen atmosphere before performing a curing process. Thus, dangling bonds are likely to be formed at hydrolyzed portions in polysilazane. Since dangling bonds are formed in advance at portions in silicon to be hydrolyzed, productivity of hydroxyl groups is enhanced. That is, since an energy required for hydrolysis is reduced, the number of the portions remaining without being hydrolyzed is reduced even when the curing process is performed at a low temperature. Therefore, dehydration synthesis occurs efficiently, which increases a crosslinking rate and makes it possible to form a dense (good film quality) insulating film.

A method of deposition is disclosed. The method can include dispensing a formable material over a substrate, where the substrate includes a non-uniform surface topography, and where the substrate includes an active zone and an exclusion zone. The method can also include curing the formable material in the exclusion zone to form a circular edge between the exclusion zone and the active zone, contacting the formable material with a superstrate, and curing the formable material in the active zone to form a layer over the substrate, wherein curing is performed while the superstrate is contacting the formable material.

Methods of bonding thin dies to substrates. In one such method, a wafer is attached to a support layer. The wafer and support layer are attached to a dicing structure and then singulated to form a plurality of semiconductor die components. Each semiconductor die component comprises a thinned die and a support layer section attached to the thinned die where each support layer section is disposed between the corresponding thinned die and the dicing structure. At least one of the semiconductor die components is then bonded to a substrate without an intervening adhesive such that the thinned die is disposed between the substrate and the support layer section. The support layer section is then removed from the thinned die.

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.