A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.

A method of positioning nanomaterials that includes forming a set of electrodes on a substrate, and covering the electrodes and substrate with a single layer of guiding dielectric material. The method may continue with patterning the guiding dielectric to provide dielectric guide features, wherein an exposed portion of the substrate between the dielectric guide features provides a deposition surface. A liquid medium containing at least one nanostructure is applied to the guiding dielectric features and the deposition surface. An electric field produced by the electrodes that is attenuated by the dielectric guide features creates an attractive force that guides the nanostructures to the deposition surface.

A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.

A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm.sup.2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

A high electron mobility heterostructure and a method of fabricating the heterostructure, wherein the high electron mobility heterostructure comprises a substrate, a buffer on the substrate, a doped charge compensation layer on the buffer, a double continuous grade barrier on the doped charge compensation layer having increasing polarization charge and decreasing polarization charge, a channel on the double continuous grade barrier, and a charge generation layer on the channel. The method comprises forming a substrate, forming a buffer on the substrate, forming a doped charge compensation layer on the buffer, forming a double continuous grade barrier on the doped charge compensation layer, forming a channel on the double continuous grade barrier, and forming a charge generation layer on the channel.

A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

A semiconductor device structure comprising: a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm, wherein an effective thermal boundary resistance (TBR.sub.eff) as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m.sup.2 K/GW with a variation of no more than 12 m.sup.2 K/GW as measured across the semiconductor device structure, and wherein the layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm.sup.2 V.sup.1 s.sup.1; and a sheet resistance of no more than 700 /square.

A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm.sup.2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

A method for creating an enhanced multipaction resistant diamond-like coating (DLC) coating with lower Secondary Electron Emission (SEE) properties is performed on an initial surface by etching a DLC coating deposited on the surface after deposition and optionally creating interlayers to enhance adhesion mechanical properties between the DLC coating and the initial surface.

A method of growing a two-dimensional transition metal dichalcogenide (TMD) thin film and a method of manufacturing a device including the two-dimensional TMD thin film are provided. The method of growing the two-dimensional TMD thin film may include a precursor supply operation and an evacuation operation, which are periodically and repeatedly performed in a reaction chamber provided with a substrate for thin film growth. The precursor supply operation may include supplying two or more kinds of precursors of a TMD material to the reaction chamber. The evacuation operation may include evacuating the two or more kinds of precursors and by-products generated therefrom from the reaction chamber.