The present invention relates to semiconductor manufacturing parts used in a dry etching process. Semiconductor manufacturing parts comprising a SiC deposition layer, of the present invention, comprises: a base material; and a SiC deposition layer formed on the surface of the base material, wherein the thickness ratio of the base material and the SiC deposition layer is 2:1 to 100:1.

Provided is a SiC chemical vapor deposition apparatus including: a furnace body inside of which a growth space is formed; and a placement table which is positioned in the growth space and has a placement surface on which a SiC wafer is placed, in which the furnace body comprises a first hole which is positioned on an upper portion which faces the placement surface and through which a raw material gas is introduced into the growth space, a second hole which is positioned on a side wall of the furnace body and through which a purge gas flows into the growth space, a third hole which is positioned on the side wall of the furnace body at a lower position than the second hole and discharges the gases in the growth space, and a protrusion which is protrudes towards the growth space from a lower end of the second hole to adjust a flow of the raw material gas.

A process for manufacturing a composite structure comprises: a) providing an initial substrate made of monocrystalline silicon carbide, b) epitaxially growing a monocrystalline silicon carbide donor layer on the initial substrate to form a donor substrate 111, c) implanting ions into the donor layer to form a buried brittle plane defining the the donor layer, d) depositing, using liquid injection-chemical vapor deposition at a temperature below 1000° C., a carrier layer on the donor layer, the carrier layer comprising an at least partially amorphous SiC matrix, e) separating the donor substrate along the brittle plane to form an intermediate composite structure comprising the donor layer on the carrier layer f) heat treating the intermediate composite structure at a temperature of between 1000° C. and 1800° C. to crystallize the carrier layer and form the polycrystalline carrier substrate, and g) applying mechanical and/or chemical treatment(s) of the composite structure.

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×10.sup.14 cm.sup.−3 and less than or equal to 5×10.sup.16 cm.sup.−3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

A method for grinding a silicon carbide wafer includes the following steps. Firstly, a single crystal is sliced into several wafers, in which each wafer has a silicon-side surface, which is the first surface. The opposite side is a carbon-side surface, which is the second surface. Subsequently, the silicon-side of the wafer is faced down and placed on a grinding stage for performing a first grinding process. It should be noted that a supporting structure exist between the wafer and the grinding stage. The supporting structure can have a concave or a convex framework. After grinding the carbon-side and removing the wafer from the stage, the wafer will appear convex or concave shape on the carbon-side surface. Thereafter, the wafer is flipped upside down and the carbon-side is placed on a flat stage without any supporting structure. Finally, the silicon-side is ground as a second grinding process.

On a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, an interlayer insulating film, first electrodes, and a second electrode are formed. Each of the first electrodes are formed by depositing a lower Ni film, an Al film, and an upper Ni film and etching the films to be apart from the interlayer insulating film; sintering the lower Ni film by a heat treatment and thereby forming a Ni silicide film; depositing a Ti film, a TiN film, and an AlSi film; and etching the AlSi film.

Disclosed herein are a III-N semiconductor structure manufactured by growing a III-N material on a superlattice structure layer, formed of AlGaN and InAlN materials, which serves as a buffer layer, and a method for manufacturing the same. The disclosed III-N semiconductor structure includes: a substrate including a silicon material; a seed layer formed on the substrate and including an aluminum nitride (AlN) material; a superlattice structure layer formed by sequentially depositing a plurality of superlattice units on the seed layer; and a cap layer formed on the superlattice structure layer and including a gallium nitride (GaN) material, wherein the superlattice units are each composed of a first layer including an AlxGa1-xN wherein 0≤x≤1 and a second layer including an InyAl1-yN wherein 0y≤0.4.

The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers. The method further includes removing the sacrificial gate structure, removing the first nano-sheet layers, and forming a gate structure around the second nano-sheet layers.

An object of the present invention is to provide a high-quality SiC semiconductor device. In order to solve the above problem, the present invention comprises a method for producing a SiC semiconductor device, comprising a growth step of forming a growth layer on a workpiece comprising SiC single crystals, a device formation step of forming at least a portion of a SiC semiconductor device in the growth layer, and a separation step of separating at least a portion of the SiC semiconductor device from the workpiece.