There is provided a nitride semiconductor laminate, including: a substrate; an electron transit layer provided on the substrate and containing a group III nitride semiconductor; and an electron supply layer provided on the electron transit layer and containing a group III nitride semiconductor, wherein a surface force A of the electron supply layer acting as an attractive force for attracting a probe and a surface of the electron supply layer when measured using the probe consisting of a glass sphere with a diameter of 1 mm covered with Cr, is stronger than a surface force B of Pt when measured under the same condition, and an absolute value |A−B| of a difference between them is 30 μN or more.

An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of Al.sub.xGa.sub.(1-x)N, Al.sub.yGa.sub.(1-y)N, and Al.sub.zGa.sub.(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a SiC single crystal substrate, the method including identifying a total number of large-pit defects caused by micropipes in the SiC single crystal substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, using microscopic and photoluminescence images. Also disclosed is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method including identifying locations of the large-pit defects caused by micropipes in the SiC single crystal substrate and the large-pit defects caused by substrate carbon inclusions in the SiC epitaxial layer, using microscopic and photoluminescence images.

A method of manufacturing a silicon carbide epitaxial substrate includes: preparing a silicon carbide single-crystal substrate having a polytype of 4H and having a principal surface inclined at an angle θ from a {0001} plane in a <11-20> direction; growing a silicon carbide epitaxial layer on the principal surface having a basal plane dislocation, the basal plane dislocation having a portion extending in a <1-100> direction and a portion extending in a <11-20> direction; and irradiating the silicon carbide epitaxial layer with an ultraviolet light having a predetermined power and a predetermined wavelength for a predetermined period of time to stabilize the basal plane dislocation. After the irradiating, the basal plane dislocation does not move even when the basal plane dislocation is irradiated with an ultraviolet light having a power of 270 mW and a wavelength of 313 nm for 10 seconds.

A silicon carbide epitaxial substrate according to a present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer disposed on the silicon carbide substrate. The silicon carbide epitaxial layer includes a boundary surface in contact with the silicon carbide substrate and a main surface opposite to the boundary surface. The main surface has an outer circumferential edge, an outer circumferential region extending within 5 mm from the outer circumferential edge, and a central region surrounded by the outer circumferential region. When an area density of double Shockley stacking faults in the outer circumferential region is defined as a first area density, and an area density of double Shockley stacking faults in the central region is defined as a second area density, the first area density is five or more times as large as the second area density, the second area density is 0.2 cm.sup.−2 or more.

A wiring substrate includes an insulating substrate including a first surface and a wiring conductor located at the insulating substrate, the insulating substrate containing multiple bulk crystallites of SiC with different polytypes. An electronic device includes the wiring substrate described above and an electronic component mounted on the wiring substrate. An electronic module includes the electronic device described above and a module substrate on which the electronic device is mounted.

A type, size, and location of a crystal defect of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected from a PL image by crystal defect inspection equipment. Detected crystal defects include a triangular polymorph stacking fault generated in the epitaxial layer during epitaxial growth and high-density BPDs extending from the stacking fault and present bundled between the stacking fault and a perfect crystal. Next, a chip region free of the triangular polymorph stacking fault and free of the high-density BPD in a specified area that is in the termination region and is located closer to a chip center than is a specified position is identified as a conforming product. A semiconductor chip set as a conforming product may contain high-density BPDs outside the specified area.

A method of manufacturing a silicon carbide semiconductor device. The method includes providing a starting substrate containing silicon carbide, epitaxially growing an epitaxial layer on the starting substrate to thereby form a semiconductor wafer, forming a plurality of scribe lines at a surface of the semiconductor wafer to delineate a plurality of chip regions, forming a mark in the epitaxial layer, the mark being formed in a marking region that is outside the scribe lines, inspecting the epitaxial layer for a crystal defect, forming a device element structure in at least one of the plurality of chip regions, dicing the semiconductor wafer into a plurality of individual semiconductor chips along the plurality of scribe lines, and identifying, as a conforming product candidate, one of the plurality of semiconductor chips that is free of the crystal defect detected during the inspecting.

Provided is a method for machining a workpiece including a substrate that has front and back surfaces and a ductile material layer that contains a ductile material and is disposed on the front or back surface. The method includes a tape bonding step of bonding a tape on a side of the substrate of the workpiece, a holding step of holding the workpiece by a holding table via the tape, and a cutting step of relatively moving the holding table and a cutting blade to cause the cutting blade to cut into the ductile material layer and the substrate. In the cutting step, the cutting blade is rotated such that a portion of the cutting blade, the portion being located on a forward side in a moving direction of the cutting blade relative to the holding table, cuts into the workpiece from the ductile material layer toward the substrate.

The present invention addresses the issue of providing: an SiC substrate having a dislocation conversion layer that can reduce resistance; and a novel technology pertaining to SiC semiconductors. This SiC substrate and SiC semiconductor device comprise a dislocation conversion layer 12 having a doping concentration of at least 1×10.sup.15 cm.sup.−3. As a result of comprising a dislocation conversion layer 12 having this kind of doping concentration: expansion of basal plane dislocations and the occurrence of high-resistance stacking faults can be suppressed; and resistance when SiC semiconductor devices are produced can be reduced.